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| pd780078, 780078y subseries 8-bit single-chip microcontrollers pd780076 pd780078 pd78f0078 pd780076y pd780078y pd78f0078y document no. u14260ej3v1ud00 (3rd edition) date published august 2004 n cp(k) printed in japan user s manual 2000, 2003
2 user? manual u14260ej3v1ud [memo] 3 user? manual u14260ej3v1ud eeprom, fip, and iebus are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices 4 user s manual u14260ej3v1ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. 5 user? manual u14260ej3v1ud the information in this document is current as of august, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 6 user s manual u14260ej3v1ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa ? a madrid, spain tel: 091-504 27 87 v ? lizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran ? aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 7 user s manual u14260ej3v1ud introduction readers this manual is intended for user engineers who wish to understand the functions of the pd780078, 780078y subseries and design and develop application systems and programs for these devices. pd780078 subseries: pd780076, 780078, 78f0078 pd780078y subseries: pd780076y, 780078y, 78f0078y purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd780078, 780078y subseries manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). pd780078, 780078y 78k/0 series subseries user s manual instructions (this manual) user s manual pin functions cpu functions internal block functions instruction set interrupts explanation of each instruction other on-chip peripheral functions electrical specifications how to read this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. to gain a general understanding of functions: read this manual in the order of the contents . the mark shows major revised points. how to interpret the register format: for a bit number enclosed in a square, the bit name is defined as a reserved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. to check the details of a register when you know the register name: refer to appendix d register index. to know the details of the 78k/0 series instruction functions: refer to the 78k/0 series instructions user s manual (u12326e) . to know the electrical specifications of the pd780078, 780078y subseries: refer to chapter 25 electrical specifications (expanded- specification products of pd780076, 780078, 78f0078) , chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) , and chapter 27 electrical specifications (conventional products) . 8 user s manual u14260ej3v1ud differences between pd780078 and 780078y subseries the configuration of the serial interface differs in pd780078 and 780078y subseries products. subseries pd780078 subseries pd780078y subseries item configuration of uart0 1 ch 1 ch serial interface uart2/sio3 1 ch 1 ch csi1 1 ch 1 ch iic0 none 1 ch chapter organization this manual divides the descriptions for the subseries into different chapters as shown below. read only the chapters related to the device you are using. chapter pd780078 subseries pd780078y subseries chapter 1 outline ( pd780078 subseries) chapter 2 outline ( pd780078y subseries) chapter 3 pin functions ( pd780078 subseries) chapter 4 pin functions ( pd780078y subseries) chapter 5 cpu architecture chapter 6 port functions chapter 7 clock generator chapter 8 16-bit timer/event counters 00, 01 chapter 9 8-bit timer/event counters 50, 51 chapter 10 watch timer chapter 11 watchdog timer chapter 12 clock output/buzzer output controller chapter 13 a/d converter chapter 14 serial interface uart0 chapter 15 serial interface uart2 chapter 16 serial interface sio3 chapter 17 serial interface csi1 chapter 18 serial interface iic0 ( pd780078y subseries only) chapter 19 interrupt functions chapter 20 external device expansion function chapter 21 standby function chapter 22 reset function chapter 23 pd78f0078, 78f0078y chapter 24 instruction set chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) chapter 27 electrical specifications (conventional products) chapter 28 package drawings chapter 29 recommended soldering conditions 9 user s manual u14260ej3v1ud conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary or b decimal hexadecimal h related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780078, 780078y subseries user s manual this manual 78k/0 series instructions user s manual u12326e 78k/0 series basics (i) application note u12704e documents related to development tools (software) (user s manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k series system simulator ver.2.30 or operation (windows tm based) u15373e later external part user open interface specifications u15802e id78k series integrated debugger ver.2.30 or later operation (windows based) u15185e project manager ver.3.12 or later (windows based) u14610e documents related to development tools (hardware) (user s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78k0-ns-pa performance board u16109e ie-780078-ns-em1 emulation board u16226e ie-78001-r-a in-circuit emulator u14142e caution the above documents are subject to change without prior notice. be sure to use the latest version of each document for designing. 10 user s manual u14260ej3v1ud documents related to flash memory programming document name document no. pg-fp3 flash memory programmer user s manual u13502e pg-fp4 flash memory programmer user s manual u15260e other documents document name document no. semiconductor selection guide products and packages x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the "semiconductor device mount manual" website (http://www.necel.com/pkg/en/mount/index.html). caution the above documents are subject to change without prior notice. be sure to use the latest version of each document for designing. 11 user? manual u14260ej3v1ud contents chapter 1 outline ( pd780078 subseries) ........................................................................ 19 1.1 expanded-specification products and conventional products ...................................... 19 1.2 features .................................................................................................................... ............ 20 1.3 applications ................................................................................................................ ......... 21 1.4 ordering information ........................................................................................................ ... 21 1.5 pin configuration (top view) .............................................................................................. 22 1.6 78k/0 series lineup ......................................................................................................... .... 24 1.7 block diagram ............................................................................................................... ....... 26 1.8 outline of functions ........................................................................................................ .... 27 1.9 mask options ................................................................................................................ ....... 28 chapter 2 outline ( pd780078y subseries) ...................................................................... 29 2.1 expanded-specification products and conventional products ...................................... 29 2.2 features .................................................................................................................... ............ 30 2.3 applications ................................................................................................................ ......... 31 2.4 ordering information ........................................................................................................ ... 31 2.5 pin configuration (top view) .............................................................................................. 32 2.6 78k/0 series lineup ......................................................................................................... .... 34 2.7 block diagram ............................................................................................................... ....... 36 2.8 outline of functions ........................................................................................................ .... 37 2.9 mask options ................................................................................................................ ....... 38 chapter 3 pin functions ( pd780078 subseries) .......................................................... 39 3.1 pin function list ........................................................................................................... ....... 39 3.2 description of pin functions .............................................................................................. 42 3.2.1 p00 to p03 (port 0) ....................................................................................................... ............ 42 3.2.2 p10 to p17 (port 1) ....................................................................................................... ............ 42 3.2.3 p20 to p25 (port 2) ....................................................................................................... ............ 42 3.2.4 p30 to p36 (port 3) ....................................................................................................... ............ 43 3.2.5 p40 to p47 (port 4) ....................................................................................................... ............ 44 3.2.6 p50 to p57 (port 5) ....................................................................................................... ............ 44 3.2.7 p64 to p67 (port 6) ....................................................................................................... ............ 44 3.2.8 p70 to p75 (port 7) ....................................................................................................... ............ 45 3.2.9 p80 (port 8) .............................................................................................................. ................. 46 3.2.10 av ref ............................................................................................................................... .......... 46 3.2.11 av ss ............................................................................................................................... ........... 46 3.2.12 reset .................................................................................................................... .................. 46 3.2.13 x1 and x2 ................................................................................................................ ................. 46 3.2.14 xt1 and xt2 .............................................................................................................. ............... 46 3.2.15 v dd0 and v dd1 ............................................................................................................................ 46 3.2.16 v ss0 and v ss1 ............................................................................................................................ 46 3.2.17 v pp (flash memory versions only) ............................................................................................. 46 12 user? manual u14260ej3v1ud 3.2.18 ic (mask rom version only) ............................................................................................... ...... 47 3.3 pin i/o circuits and recommended connection of unused pins ................................... 48 chapter 4 pin functions ( pd780078y subseries) ......................................................... 52 4.1 pin function list ........................................................................................................... ....... 52 4.2 description of pin functions .............................................................................................. 55 4.2.1 p00 to p03 (port 0) ....................................................................................................... ............ 55 4.2.2 p10 to p17 (port 1) ....................................................................................................... ............ 55 4.2.3 p20 to p25 (port 2) ....................................................................................................... ............ 55 4.2.4 p30 to p36 (port 3) ....................................................................................................... ............ 56 4.2.5 p40 to p47 (port 4) ....................................................................................................... ............ 57 4.2.6 p50 to p57 (port 5) ....................................................................................................... ............ 57 4.2.7 p64 to p67 (port 6) ....................................................................................................... ............ 57 4.2.8 p70 to p75 (port 7) ....................................................................................................... ............ 58 4.2.9 p80 (port 8) .............................................................................................................. ................. 59 4.2.10 av ref ............................................................................................................................... .......... 59 4.2.11 av ss ............................................................................................................................... ........... 59 4.2.12 reset .................................................................................................................... .................. 59 4.2.13 x1 and x2 ................................................................................................................ ................. 59 4.2.14 xt1 and xt2 .............................................................................................................. ............... 59 4.2.15 v dd0 and v dd1 ............................................................................................................................ 59 4.2.16 v ss0 and v ss1 ............................................................................................................................ 59 4.2.17 v pp (flash memory versions only) ............................................................................................. 59 4.2.18 ic (mask rom version only) ............................................................................................... ...... 60 4.3 pin i/o circuits and recommended connection of unused pins ................................... 61 chapter 5 cpu architecture ................................................................................................ 6 4 5.1 memory spaces ............................................................................................................... ..... 64 5.1.1 internal program memory space ............................................................................................. .. 67 5.1.2 internal data memory space ................................................................................................ ..... 68 5.1.3 special function register (sfr) area ...................................................................................... ... 68 5.1.4 external memory space ..................................................................................................... ....... 68 5.1.5 data memory addressing .................................................................................................... ...... 69 5.2 processor registers ......................................................................................................... ... 72 5.2.1 control registers ......................................................................................................... ............... 72 5.2.2 general-purpose registers ................................................................................................. ....... 75 5.2.3 special function registers (sfr) .......................................................................................... ..... 77 5.3 instruction address addressing ........................................................................................ 81 5.3.1 relative addressing ....................................................................................................... ............ 81 5.3.2 immediate addressing ...................................................................................................... ......... 82 5.3.3 table indirect addressing ................................................................................................. ......... 83 5.3.4 register addressing ....................................................................................................... ........... 84 5.4 operand address addressing ............................................................................................ 85 5.4.1 implied addressing ........................................................................................................ ............ 85 5.4.2 register addressing ....................................................................................................... ........... 86 5.4.3 direct addressing ......................................................................................................... ............. 87 13 user? manual u14260ej3v1ud 5.4.4 short direct addressing ................................................................................................... .......... 88 5.4.5 special function register (sfr) addressing ............................................................................... 8 9 5.4.6 register indirect addressing .............................................................................................. ........ 90 5.4.7 based addressing .......................................................................................................... ........... 91 5.4.8 based indexed addressing .................................................................................................. ...... 92 5.4.9 stack addressing .......................................................................................................... ............. 93 chapter 6 port functions ................................................................................................... .. 94 6.1 port functions .............................................................................................................. ........ 94 6.2 port configuration .......................................................................................................... ..... 97 6.2.1 port 0 .................................................................................................................... ..................... 97 6.2.2 port 1 .................................................................................................................... ..................... 99 6.2.3 port 2 .................................................................................................................... ..................... 100 6.2.4 port 3 ( pd780078 subseries) ................................................................................................. 104 6.2.5 port 3 ( pd780078y subseries) ............................................................................................... 107 6.2.6 port 4 .................................................................................................................... ..................... 110 6.2.7 port 5 .................................................................................................................... ..................... 112 6.2.8 port 6 .................................................................................................................... ..................... 113 6.2.9 port 7 .................................................................................................................... ..................... 115 6.2.10 port 8 ................................................................................................................... ...................... 117 6.3 port function control registers ........................................................................................ 118 6.4 port function operations .................................................................................................... 125 6.4.1 writing to i/o port ....................................................................................................... ............... 125 6.4.2 reading from i/o port ..................................................................................................... .......... 125 6.4.3 operations on i/o port .................................................................................................... .......... 125 6.5 selection of mask option .................................................................................................... 126 chapter 7 clock generator ................................................................................................ 12 7 7.1 clock generator functions ................................................................................................. 12 7 7.2 clock generator configuration .......................................................................................... 127 7.3 clock generator control registers .................................................................................... 129 7.4 system clock oscillator ..................................................................................................... . 133 7.4.1 main system clock oscillator .............................................................................................. ........ 133 7.4.2 subsystem clock oscillator ................................................................................................ ........ 134 7.4.3 when subsystem clock is not used .......................................................................................... . 137 7.5 clock generator operations ............................................................................................... 138 7.5.1 main system clock operations .............................................................................................. ..... 139 7.5.2 subsystem clock operations ................................................................................................ ..... 140 7.6 changing system clock and cpu clock settings ............................................................ 140 7.6.1 time required for switchover between system clock and cpu clock ........................................ 140 7.6.2 system clock and cpu clock switching procedure ................................................................... 141 chapter 8 16-bit timer/event counters 00, 01 ............................................................. 142 8.1 functions of 16-bit timer/event counters 00, 01 ............................................................. 142 8.2 configuration of 16-bit timer/event counters 00, 01 ....................................................... 143 14 user? manual u14260ej3v1ud 8.3 registers to control 16-bit timer/event counters 00, 01 ................................................ 148 8.4 operation of 16-bit timer/event counters 00, 01 ............................................................. 158 8.4.1 interval timer operation .................................................................................................. ........... 158 8.4.2 external event counter operation .......................................................................................... .... 161 8.4.3 pulse width measurement operations ....................................................................................... 1 63 8.4.4 square-wave output operation .............................................................................................. .... 171 8.4.5 ppg output operation ...................................................................................................... .......... 173 8.5 program list ................................................................................................................ ......... 176 8.5.1 interval timer ............................................................................................................ ................. 177 8.5.2 pulse width measurement by free-running counter and one capture register ........................... 178 8.5.3 two pulse widths measurement by free-running counter .......................................................... 179 8.5.4 pulse width measurement by restart ........................................................................................ . 181 8.5.5 ppg output ................................................................................................................ ................ 182 8.6 cautions for 16-bit timer/event counters 00, 01 ............................................................. 183 chapter 9 8-bit timer/event counters 50, 51 ............................................................... 187 9.1 functions of 8-bit timer/event counters 50, 51 ............................................................... 187 9.2 configuration of 8-bit timer/event counters 50, 51 ......................................................... 189 9.3 registers to control 8-bit timer/event counters 50, 51 .................................................. 191 9.4 operation of 8-bit timer/event counters 50, 51 ............................................................... 196 9.4.1 8-bit interval timer operation ............................................................................................ .......... 196 9.4.2 external event counter operation .......................................................................................... .... 199 9.4.3 square-wave output (8-bit resolution) operation ....................................................................... 200 9.4.4 8-bit pwm output operation ................................................................................................ ...... 201 9.4.5 interval timer (16-bit) operations ........................................................................................ ....... 205 9.5 program list ................................................................................................................ ......... 206 9.5.1 interval timer (8-bit) .................................................................................................... ............... 206 9.5.2 external event counter .................................................................................................... .......... 207 9.5.3 interval timer (16-bit) ................................................................................................... .............. 208 9.6 cautions for 8-bit timer/event counters 50, 51 ............................................................... 209 chapter 10 watch timer ..................................................................................................... .... 210 10.1 watch timer functions ...................................................................................................... . 210 10.2 watch timer configuration ................................................................................................. 2 11 10.3 register to control watch timer ........................................................................................ 211 10.4 watch timer operations ..................................................................................................... 213 10.4.1 watch timer operation .................................................................................................... ........... 213 10.4.2 interval timer operation ................................................................................................. ............ 213 10.5 cautions for watch timer ................................................................................................... 214 chapter 11 watchdog timer ................................................................................................. 2 15 11.1 watchdog timer functions ................................................................................................. 21 5 11.2 watchdog timer configuration .......................................................................................... 216 11.3 registers to control watchdog timer ............................................................................... 216 11.4 watchdog timer operations ............................................................................................... 218 15 user? manual u14260ej3v1ud 11.4.1 watchdog timer operation ................................................................................................. ........ 218 11.4.2 interval timer operation ................................................................................................. ............ 219 chapter 12 clock output/buzzer output controller ........................................... 220 12.1 clock output/buzzer output controller functions .......................................................... 220 12.2 configuration of clock output/buzzer output controller ................................................ 221 12.3 registers to control clock output/buzzer output controller ......................................... 221 12.4 operation of clock output/buzzer output controller ...................................................... 224 12.4.1 operation as clock output ................................................................................................ ......... 224 12.4.2 operation as buzzer output ............................................................................................... ........ 224 chapter 13 a/d converter ................................................................................................... .. 225 13.1 a/d converter functions .................................................................................................... . 225 13.2 a/d converter configuration .............................................................................................. 22 6 13.3 registers used in a/d converter ....................................................................................... 228 13.4 a/d converter operation .................................................................................................... . 232 13.4.1 basic operations of a/d converter ........................................................................................ ..... 232 13.4.2 input voltage and conversion results ..................................................................................... .... 234 13.4.3 a/d converter operation mode ............................................................................................. ..... 235 13.5 how to read a/d converter characteristics table ........................................................... 238 13.6 cautions for a/d converter ................................................................................................. 241 chapter 14 serial interface uart0 .................................................................................. 247 14.1 functions of serial interface uart0 .................................................................................. 247 14.2 configuration of serial interface uart0 ........................................................................... 249 14.3 registers to control serial interface uart0 ..................................................................... 250 14.4 operation of serial interface uart0 .................................................................................. 255 14.4.1 operation stop mode ...................................................................................................... ........... 255 14.4.2 asynchronous serial interface (uart) mode ............................................................................ 255 14.4.3 infrared data transfer mode .............................................................................................. ......... 264 chapter 15 serial interface uart2 .................................................................................. 268 15.1 functions of serial interface uart2 .................................................................................. 268 15.2 configuration of serial interface uart2 ........................................................................... 270 15.3 registers to control serial interface uart2 ..................................................................... 272 15.4 operation of serial interface uart2 .................................................................................. 281 15.4.1 operation stop mode ...................................................................................................... ........... 281 15.4.2 asynchronous serial interface (uart) mode ............................................................................ 282 15.4.3 multi-processor transfer mode ............................................................................................ ...... 297 15.4.4 infrared data transfer (irda) mode ....................................................................................... ..... 303 chapter 16 serial interface sio3 ...................................................................................... 310 16.1 functions of serial interface sio3 ..................................................................................... 310 16 user? manual u14260ej3v1ud 16.2 configuration of serial interface sio3 ............................................................................... 311 16.3 registers to control serial interface sio3 ........................................................................ 311 16.4 operation of serial interface sio3 ...................................................................................... 314 16.4.1 operation stop mode ...................................................................................................... ........... 314 16.4.2 3-wire serial i/o mode ................................................................................................... ............ 315 chapter 17 serial interface csi1 ...................................................................................... 318 17.1 functions of serial interface csi1 ...................................................................................... 318 17.2 configuration of serial interface csi1 ............................................................................... 318 17.3 registers to control serial interface csi1 ......................................................................... 319 17.4 operation of serial interface csi1 ...................................................................................... 323 17.4.1 operation stop mode ...................................................................................................... ........... 323 17.4.2 3-wire serial i/o mode ................................................................................................... ............ 323 chapter 18 serial interface iic0 ( pd780078y subseries only) ........................... 333 18.1 functions of serial interface iic0 ....................................................................................... 33 3 18.2 configuration of serial interface iic0 ................................................................................. 336 18.3 registers to control serial interface iic0 .......................................................................... 338 18.4 i 2 c bus mode functions ..................................................................................................... 348 18.4.1 pin configuration ........................................................................................................ ............... 348 18.5 i 2 c bus definitions and control methods ......................................................................... 349 18.5.1 start conditions ......................................................................................................... ................ 349 18.5.2 addresses ................................................................................................................ ................. 350 18.5.3 transfer direction specification ......................................................................................... ......... 350 18.5.4 acknowledge (ack) signal ................................................................................................. ....... 351 18.5.5 stop condition ........................................................................................................... ................ 352 18.5.6 wait signal (wait) ....................................................................................................... ............. 353 18.5.7 interrupt request (intiic0) generation timing and wait control ................................................. 355 18.5.8 address match detection method ........................................................................................... .. 356 18.5.9 error detection .......................................................................................................... ................. 356 18.5.10 extension code .......................................................................................................... ................ 356 18.5.11 arbitration ............................................................................................................. ..................... 357 18.5.12 wake-up function ........................................................................................................ .............. 358 18.5.13 communication reservation ............................................................................................... ....... 359 18.5.14 other cautions .......................................................................................................... ................. 361 18.5.15 communication operations ................................................................................................ ....... 362 18.5.16 timing of i 2 c interrupt request (intiic0) occurrence ............................................................... 370 18.6 timing charts .............................................................................................................. ......... 388 chapter 19 interrupt functions ........................................................................................ 395 19.1 interrupt function types ................................................................................................... .. 395 19.2 interrupt sources and configuration ................................................................................. 395 19.3 interrupt function control registers ................................................................................. 400 19.4 interrupt servicing operations ........................................................................................... 40 6 19.4.1 non-maskable interrupt request acknowledgment operation .................................................... 406 17 user? manual u14260ej3v1ud 19.4.2 maskable interrupt request acknowledgment operation ............................................................ 409 19.4.3 software interrupt request acknowledgment operation ............................................................. 411 19.4.4 multiple interrupt servicing ............................................................................................. ........... 412 19.4.5 interrupt request hold ................................................................................................... ............. 415 chapter 20 external device expansion function ..................................................... 416 20.1 external device expansion function ................................................................................. 416 20.2 external device expansion function control registers .................................................. 418 20.3 external device expansion function timing .................................................................... 420 20.4 example of connection with memory ................................................................................ 425 chapter 21 standby function .............................................................................................. 42 6 21.1 standby function and configuration ................................................................................. 426 21.1.1 standby function ......................................................................................................... .............. 426 21.1.2 standby function control register ........................................................................................ ....... 427 21.2 standby function operations ............................................................................................. 428 21.2.1 halt mode ................................................................................................................ ............... 428 21.2.2 stop mode ................................................................................................................ .............. 431 chapter 22 reset function .................................................................................................. . 434 22.1 reset function ............................................................................................................. ........ 434 chapter 23 pd78f0078, 78f0078y ............................................................................................. 438 23.1 memory size switching register ........................................................................................ 439 23.2 internal expansion ram size switching register ............................................................ 440 23.3 flash memory characteristics ............................................................................................ 441 23.3.1 programming environment .................................................................................................. ...... 441 23.3.2 communication mode ....................................................................................................... ........ 442 23.3.3 on-board pin processing .................................................................................................. ......... 445 23.3.4 connection of adapter for flash writing .................................................................................. .... 448 chapter 24 instruction set ................................................................................................. . 452 24.1 legend used in operation list ........................................................................................... 453 24.1.1 operand identifiers and specification methods ......................................................................... 453 24.1.2 description of ?peration column ........................................................................................ ..... 454 24.1.3 description of ?lag operation column ................................................................................... .... 454 24.2 operation list ............................................................................................................. .......... 455 24.3 instructions listed by addressing type ........................................................................... 463 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) ................................................... 467 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) ............................................ 498 18 user? manual u14260ej3v1ud chapter 27 electrical specifications (conventional products) ..................... 527 chapter 28 package drawings .............................................................................................. 556 chapter 29 recommended soldering conditions ......................................................... 559 appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries .......................................................................................... 561 appendix b development tools .......................................................................................... 564 b.1 software package ............................................................................................................ .... 567 b.2 language processing software ......................................................................................... 567 b.3 control software ............................................................................................................ ...... 568 b.4 flash memory writing tools ............................................................................................... 568 b.5 debugging tools (hardware) .............................................................................................. 569 b.5.1 when using the in-circuit emulator ie-78k0-ns or ie-78k0-ns-a ............................................ 569 b.5.2 when using the in-circuit emulator ie-78001-r-a ..................................................................... 570 b.6 debugging tools (software) ............................................................................................... 571 appendix c notes on target system design ................................................................... 575 appendix d register index .................................................................................................. ... 580 d.1 register index (in alphabetical order with respect to register names) ....................... 580 d.2 register index (in alphabetical order with respect to register symbol) ..................... 583 appendix e revision history ................................................................................................ . 586 e.1 major revisions in this edition .......................................................................................... 586 e.2 revision history up to previous edition ........................................................................... 589 19 user? manual u14260ej3v1ud chapter 1 outline ( pd780078 subseries) 1.1 expanded-specification products and conventional products the expanded-specification products and conventional products refer to the following products. expanded-specification products: products with a rank note other than k mask rom and flash memory versions for which orders were received on or after february 1, 2002 conventional products: products with rank note k products other than the above expanded-specification products note the rank is indicated by the 5th digit from the left in the lot number marked on the package. expanded-specification products and conventional products differ in the operating frequency ratings. table 1-1 shows the differences between these products. table 1-1. differences between expanded-specification products and conventional products power supply voltage (v dd ) guaranteed operating speed (operating frequency) conventional products expanded-specification products 4.5 to 5.5 v 8.38 mhz (0.238 s) 12 mhz (0.166 s) 4.0 to 5.5 v 8.38 mhz (0.238 s) 8.38 mhz (0.238 s) 3.0 to 5.5 v 5 mhz (0.4 s) 8.38 mhz (0.238 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the parenthesized values indicate the minimum instruction execution time. lot number year code rank week code 20 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud 1.2 features minimum instruction execution time changeable from high speed (expanded-specification products 0.166 s: @ 12 mhz operation with main system clock, conventional products 0.238 s: @ 8.38 mhz operation with main system clock) to ultra-low speed (122 s: @ 32.768 khz operation with subsystem clock) general-purpose registers: 8 bits 32 registers (8 bits 8 registers 4 banks) internal memory type program memory data memory part number (rom) high-speed ram expansion ram pd780076 mask rom 48 kb 1024 bytes 1024 bytes pd780078 60 kb pd78f0078 flash memory 60 kb note note the capacity of the internal flash memory can be changed by means of the memory size switching register (ims). external memory expansion space: 64 kb (on-chip external device expansion function) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions 52 i/o ports: (four n-ch open-drain ports) timer: 6 channels 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel serial interface: 3 channels 3-wire serial i/o mode: 1 channel uart mode: 1 channel 3-wire serial i/o/uart mode selectable: 1 channel 10-bit resolution a/d converter: 8 channels vectored interrupt sources: 25 two types of on-chip clock oscillators (main system clock and subsystem clock) power supply voltage: v dd = 1.8 to 5.5 v 21 chapter 1 outline ( pd780078 subseries) user? manual u14260ej3v1ud 1.3 applications personal computers, air conditioners, dashboards, car audio, etc. 1.4 ordering information part number package internal rom pd780076gc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780076gc- -ab8 64-pin plastic qfp (14 14) mask rom pd780076gk- -9et 64-pin plastic tqfp (12 12) mask rom pd780078gc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780078gc- -ab8 64-pin plastic qfp (14 14) mask rom pd780078gk- -9et 64-pin plastic tqfp (12 12) mask rom pd78f0078gc-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0078gc-ab8 64-pin plastic qfp (14 14) flash memory pd78f0078gk-9et 64-pin plastic tqfp (12 12) flash memory remark indicates rom code suffix. 22 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud 1.5 pin configuration (top view) 64-pin plastic lqfp (14 14) 64-pin plastic qfp (14 14) 64-pin plastic tqfp (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32 p33 p34/si3/t x d2 p35/so3/r x d2 p71/ti010 p70/ti000/to00 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset p80/ss1 av ref p10/ani0 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz/ti001/to01 p74/pcl/ti011 p73/ti51/to51 p72/ti50/to50 p36/sck3/asck2 p20/si1 p21/so1 p22/sck1 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the pd78f0078. 23 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud pcl: programmable clock rd: read strobe reset: reset r x d0, r x d2: receive data sck1, sck3: serial clock si1, si3: serial input so1, so3: serial output ss1: serial interface chip select input ti000, ti010, ti001, ti011, ti50, ti51: timer input to00, to01, to50, to51: timer output t x d0, t x d2: transmit data v dd0 , v dd1 : power supply v pp : programming power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input asck0, asck2: asynchronous serial clock astb: address strobe av ref : analog reference voltage av ss : analog ground buz: buzzer clock ic: internally connected intp0 to intp3: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p25: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 p70 to p75: port 7 p80: port 8 24 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud 1.6 78k/0 series lineup the 78k/0 series product lineup is illustrated below. part numbers in the boxes indicate subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703ay pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y 25 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud the major functional differences between the subseries are shown below. subseries without the suffix y function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 kb to 40 kb 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v yes pd78078 48 kb to 60 kb pd78070a 61 2.7 v pd780058 24 kb to 60 kb 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 kb to 60 kb 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 kb to 60 kb 2.0 v pd780065 40 kb to 48 kb 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 kb to 60 kb 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 kb to 32 kb 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd780034as 4 ch 39 pd780024as 4 ch pd78014h 8 ch 2 ch 53 yes pd78018f 8 kb to 60 kb pd78083 8 kb to 16 kb 1 ch (uart: 1 ch) 33 inverter pd780988 16 kb to 60 kb 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v yes control vfd pd780208 32 kb to 60 kb 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 kb to 24 kb 3 ch 4 ch 40 4.5 v pd78044h 32 kb to 48 kb 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 kb to 40 kb 2 ch lcd pd780354 24 kb to 32 kb 4 ch 1 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 66 1.8 v drive pd780344 8 ch pd780338 48 kb to 60 kb 3 ch 2 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 pd780328 62 pd780318 70 pd780308 48 kb to 60 kb 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 kb 2 ch (uart: 1 ch) pd78064 16 kb to 32 kb bus pd780948 60 kb 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v yes interface pd78098b 40 kb to 60 kb 1 ch 2 ch 69 2.7 v supported pd780816 32 kb to 60 kb 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter control pd780958 48 kb to 60 kb 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v dashboard pd780852 32 kb to 40 kb 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v control pd780828b 32 kb to 60 kb 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value 26 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud 1.7 block diagram remarks 1. the internal rom capacities differ depending on the product. 2. pin connection in parentheses is intended for the pd78f0078. 16-bit timer/ event counter 00 ti000/to00/p70 ti010/p71 serial interface csi1 si1/p20 so1/p21 sck1/p22 serial interface sio3 si3/p34 so3/p35 sck3/p36 rxd0/p23 txd0/p24 asck0/p25 ani0/p10 to ani7/p17 uart0 interrupt control 16-bit timer/ event counter 01 ti001/to01/p75 ti011/p74 8-bit timer/ event counter 50 ti50/to50/p72 ti51/to51/p73 8-bit timer/ event counter 51 watch timer watchdog timer 8 a/d converter 78k/0 cpu core internal high-speed ram 1024 bytes internal expansion ram 1024 bytes rom flash memory port 0 p00 to p03 4 port 1 p10 to p17 port 2 p20 to p25 6 port 3 p30 to p36 7 port 4 p40 to p47 8 port 5 p50 to p57 8 port 6 p64 to p67 4 port 7 p70 to p75 6 port 8 external access p80 wr/p65 a8/p50 to a15/p57 rd/p64 wait/p66 system control reset x1 8 ad0/p40 to ad7/p47 x2 xt1 xt2 8 rxd2/p35 txd2/p34 asck2/p36 uart2 ss1/p80 v dd1 v ss0 ic (v pp ) v dd0 v ss1 wr/p65 astb/p67 8 clock/buzzer output control pcl/p74 buz/p75 adtrg/p03 av ref av ss intp0/p00 to intp3/p03 4 27 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud 1.8 outline of functions part number pd780076 pd780078 pd78f0078 item internal memory rom 48 kb 60 kb 60 kb note 1 (mask rom) (mask rom) (flash memory) high-speed ram 1024 bytes expansion ram 1024 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time selection function execution time when main system 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 mhz operation, expanded- clock selected specification products only) 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@ 8.38 mhz operation) when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 52 cmos input: 8 cmos i/o: 40 n-ch open-drain i/o (5 v tolerant): 4 timer 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output 4 outputs (8-bit pwm output enabled: 2) clock output 93.7 khz, 187 khz, 375 khz, 750 khz, 1.5 mhz, 3 mhz, 6 mhz, 12 mhz (12 mhz with main system clock, expanded-specification products only) 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.46 khz, 2.92 khz, 5.85 khz, 11.7 khz (12 mhz with main system clock, expanded-specification products only) 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) a/d converter 10-bit resolution 8 channels low-voltage operation: av ref = 2.2 to 5.5 v serial interface 3-wire serial i/o mode: 1 channel uart mode: 1 channel 3-wire serial i/o/uart mode selectable note 2 : 1 channel vectored interrupt maskable internal: 18, external: 5 source non-maskable internal: 1 software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = 40 to +85 c package 64-pin plastic lqfp (14 14) 64-pin plastic qfp (14 14) 64-pin plastic tqfp (12 12) notes 1. the capacity of the internal flash memory can be changed by means of the memory size switching register (ims). 2. select either of the functions of these alternate-function pins. 28 chapter 1 outline ( pd780078 subseries) user s manual u14260ej3v1ud the following table outlines the timer/event counters (for details, refer to chapter 8 16-bit timer/event counters 00, 01, chapter 9 8-bit timer/event counters 50, 51, chapter 10 watch timer, and chapter 11 watchdog timer) . 16-bit timer/event 8-bit timer/event watch timer watchdog timer counters 00, 01 counters 50, 51 tm00 tm01 tm50 tm51 operation interval timer 1 channel 1 channel 1 channel 1 channel 1 channel note 1 1 channel note 2 mode external event counter 1 channel 1 channel 1 channel 1 channel function timer output 1 output 1 output 1 output 1 output ppg output 1 output 1 output pwm output 1 output 1 output pulse width measurement 2 inputs 2 inputs square wave output 1 output 1 output 1 output 1 output interrupt source 2 2 1 1 1 1 note 3 notes 1. the watch timer can be used both as a watch timer and an interval timer at the same time. 2. the watchdog timer can be used as either a watchdog timer or interval timer. select one of the functions. 3. a non-maskable interrupt or maskable interrupt (internal) can be selected for the watchdog timer interrupt (intwdt). 1.9 mask options the mask rom versions ( pd780076 and 780078) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. using the mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the pd780078 subseries are shown in table 1-2. table 1-2. mask options of mask rom versions pin name mask option p30 to p33 pull-up resistor connection can be specified in 1-bit units. 29 user? manual u14260ej3v1ud chapter 2 outline ( pd780078y subseries) 2.1 expanded-specification products and conventional products the expanded-specification products and conventional products refer to the following products. expanded-specification products: products with a rank note other than k mask rom and flash memory versions for which orders were received on or after february 1, 2002 conventional products: products with rank note k products other than the above expanded-specification products note the rank is indicated by the 5th digit from the left in the lot number marked on the package. expanded-specification products and conventional products differ in the operating frequency ratings. table 2-1 shows the differences between these products. table 2-1. differences between expanded-specification products and conventional products power supply voltage (v dd ) guaranteed operating speed (operating frequency) conventional products expanded-specification products 4.0 to 5.5 v 8.38 mhz (0.238 s) 8.38 mhz (0.238 s) 3.0 to 5.5 v 5 mhz (0.4 s) 8.38 mhz (0.238 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the parenthesized values indicate the minimum instruction execution time. lot number year code rank week code 30 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud 2.2 features minimum instruction execution time changeable from high speed (0.238 s: @ 8.38 mhz operation with main system clock) to ultra-low speed (122 s: @ 32.768 khz operation with subsystem clock) general-purpose registers: 8 bits 32 registers (8 bits 8 registers 4 banks) internal memory type program memory data memory part number (rom) high-speed ram expansion ram pd780076y mask rom 48 kb 1024 bytes 1024 bytes pd780078y 60 kb pd78f0078y flash memory 60 kb note note the capacity of the internal flash memory can be changed by means of the memory size switching register (ims). external memory expansion space: 64 kb (on-chip external device expansion function) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions 52 i/o ports: (four n-ch open-drain ports) timer: 6 channels 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel serial interface: 4 channels 3-wire serial mode: 1 channel uart mode: 1 channel 3-wire serial i/o/uart mode selectable: 1 channel i 2 c mode: 1 channel 10-bit resolution a/d converter: 8 channels vectored interrupt sources: 26 two types of on-chip clock oscillators (main system clock and subsystem clock) power supply voltage: v dd = 1.8 to 5.5 v 31 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud 2.3 applications personal computers, air conditioners, dashboards, car audio, etc. 2.4 ordering information part number package internal rom pd780076ygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780076ygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780076ygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780078ygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780078ygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780078ygk- -9et 64-pin plastic tqfp (12 12) mask rom pd78f0078ygc-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0078ygc-ab8 64-pin plastic qfp (14 14) flash memory pd78f0078ygk-9et 64-pin plastic tqfp (12 12) flash memory remark indicates rom code suffix. 32 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud 2.5 pin configuration (top view) 64-pin plastic lqfp (14 14) 64-pin plastic qfp (14 14) 64-pin plastic tqfp (12 12) cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying v dd0 and v dd1 independently, connecting v ss0 and v ss1 independently to ground lines, and so on. 2. pin connection in parentheses is intended for the pd78f0078y. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34/si3/t x d2 p35/so3/r x d2 p36/sck3/asck2 p20/si1 p21/so1 p22/sck1 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p71/ti010 p70/ti000/to00 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset p80/ss1 av ref p10/ani0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz/ti001/to01 p74/pcl/ti011 p73/ti51/to51 p72/ti50/to50 33 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud pcl: programmable clock rd: read strobe reset: reset r x d0, r x d2: receive data sck1, sck3, scl0: serial clock sda0: serial data si1, si3: serial input so1, so3: serial output ss1: serial interface chip select input ti000, ti010, ti001, ti011, ti50, ti51: timer input to00, to01, to50, to51: timer output t x d0, t x d2: transmit data v dd0 , v dd1 : power supply v pp : programming power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input asck0, asck2: asynchronous serial clock astb: address strobe av ref : analog reference voltage av ss : analog ground buz: buzzer clock ic: internally connected intp0 to intp3: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p25: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 p70 to p75: port 7 p80: port 8 34 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud 2.6 78k/0 series lineup the 78k/0 series product lineup is illustrated below. part numbers in the boxes indicate subseries names. remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703ay pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y 35 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud the major functional differences between the subseries are shown below. subseries with the suffix y function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a min. value expansion control pd78078y 48 kb to 60 kb 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, 88 1.8 v yes pd78070ay i 2 c: 1 ch) 61 2.7 v pd780018ay 48 kb to 60 kb 3 ch (i 2 c: 1 ch) 88 pd780058y 24 kb to 60 kb 2 ch 2 ch 3 ch (time-division 68 1.8 v uart: 1 ch, i 2 c: 1 ch) pd78058fy 48 kb to 60 kb 3 ch (uart: 1 ch, 69 2.7 v pd78054y 16 kb to 60 kb i 2 c: 1 ch) 2.0 v pd780078y 48 kb to 60 kb 2 ch 8 ch 4 ch (uart: 2 ch, 52 1.8 v i 2 c: 1 ch) pd780034ay 8 kb to 32 kb 1 ch 3 ch (uart: 1 ch, 51 pd780024ay 8 ch i 2 c: 1 ch) pd78018fy 8 kb to 60 kb 2 ch (i 2 c: 1 ch) 53 lcd pd780354y 24 kb to 32 kb 4 ch 1 ch 1 ch 1 ch 8 ch 4 ch (uart: 1 ch, 66 1.8 v drive pd780344y 8 ch i 2 c: 1 ch) pd780308y 48 kb to 60 kb 2 ch 3 ch (time-division 57 2.0 v uart: 1 ch, i 2 c: 1 ch) pd78064y 16 kb to 32 kb 2 ch (uart: 1 ch, i 2 c: 1 ch) bus pd780702y 60 kb 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, 67 3.5 v interface pd780703ay 59.5 kb i 2 c: 1 ch) supported pd780833y 60 kb 65 4.5 v remark the functions of the subseries without the suffix y and the subseries with the suffix y are the same, except for the serial interface (if a subseries without the suffix y is available). 36 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud 2.7 block diagram remarks 1. the internal rom capacities differ depending on the product. 2. pin connection in parentheses is intended for the pd78f0078y. 16-bit timer/ event counter 00 ti000/to00/p70 ti010/p71 serial interface csi1 si1/p20 so1/p21 sck1/p22 serial interface sio3 si3/p34 so3/p35 sck3/p36 rxd0/p23 txd0/p24 asck0/p25 ani0/p10 to ani7/p17 i 2 c bus uart0 interrupt control scl0/p33 sda0/p32 16-bit timer/ event counter 01 ti001/to01/p75 ti011/p74 8-bit timer/ event counter 50 ti50/to50/p72 ti51/to51/p73 8-bit timer/ event counter 51 watch timer watchdog timer 8 a/d converter 78k/0 cpu core internal high-speed ram 1024 bytes internal expansion ram 1024 bytes port 0 p00 to p03 4 port 1 p10 to p17 port 2 p20 to p25 6 port 3 p30 to p36 7 port 4 p40 to p47 8 port 5 p50 to p57 8 port 6 p64 to p67 4 port 7 p70 to p75 6 port 8 external access p80 wr/p65 a8/p50 to a15/p57 rd/p64 wait/p66 system control reset x1 8 ad0/p40 to ad7/p47 x2 xt1 xt2 8 rxd2/p35 txd2/p34 asck2/p36 uart2 ss1/p80 v dd1 v ss0 ic (v pp ) v dd0 v ss1 wr/p65 astb/p67 8 clock/buzzer output control pcl/p74 buz/p75 adtrg/p03 av ref av ss intp0/p00 to intp3/p03 4 rom flash memory 37 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud 2.8 outline of functions part number pd780076y pd780078y pd78f0078y item internal memory rom 48 kb 60 kb 60 kb note 1 (mask rom) (mask rom) (flash memory) high-speed ram 1024 bytes expansion ram 1024 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time selection function execution time when main system 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@ 8.38 mhz operation) clock selected when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 52 cmos input: 8 cmos i/o: 40 n-ch open-drain i/o (5 v tolerant): 4 timer 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output 4 outputs (8-bit pwm output enabled: 2) clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) a/d converter 10-bit resolution 8 channels low-voltage operation: av ref = 2.2 to 5.5 v serial interface 3-wire serial i/o mode: 1 channel uart mode: 1 channel 3-wire serial i/o/uart mode selectable note 2 : 1 channel i 2 c bus mode: 1 channel vectored interrupt maskable internal: 19, external: 5 source non-maskable internal: 1 software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = 40 to +85 c package 64-pin plastic lqfp (14 14) 64-pin plastic qfp (14 14) 64-pin plastic tqfp (12 12) notes 1. the capacity of the internal flash memory can be changed by means of the memory size switching register (ims). 2. select either of the functions of these alternate-function pins. 38 chapter 2 outline ( pd780078y subseries) user s manual u14260ej3v1ud the following table outlines the timer/event counters (for details, refer to chapter 8 16-bit timer/event counters 00, 01, chapter 9 8-bit timer/event counters 50, 51, chapter 10 watch timer, and chapter 11 watchdog timer) . 16-bit timer/event 8-bit timer/event watch timer watchdog timer counters 00, 01 counters 50, 51 tm00 tm01 tm50 tm51 operation interval timer 1 channel 1 channel 1 channel 1 channel 1 channel note 1 1 channel note 2 mode external event counter 1 channel 1 channel 1 channel 1 channel function timer output 1 output 1 output 1 output 1 output ppg output 1 output 1 output pwm output 1 output 1 output pulse width measurement 2 inputs 2 inputs square wave output 1 output 1 output 1 output 1 output interrupt source 2 2 1 1 1 1 note 3 notes 1. the watch timer can be used both as a watch timer and an interval timer at the same time. 2. the watchdog timer can be used as either a watchdog timer or interval timer. select one of the functions. 3. a non-maskable interrupt or maskable interrupt (internal) can be selected for the watchdog timer interrupt (intwdt). 2.9 mask options the mask rom versions ( pd780076y and 780078y) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the pd780078y subseries are shown in table 2-2. table 2-2. mask options of mask rom versions pin name mask option p30 and p31 pull-up resistor connection can be specified in 1-bit units. 39 user? manual u14260ej3v1ud pin name i/o function after reset alternate function p00 i/o input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input-only port. p20 i/o input si1 p21 so1 p22 sck1 p23 rxd0 p24 txd0 p25 asck0 p30 i/o input p31 p32 p33 p34 si3/t x d2 p35 so3/r x d2 p36 sck3/asck2 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. p64 i/o input rd p65 wr p66 wait p67 astb chapter 3 pin functions ( pd780078 subseries) 3.1 pin function list (1) port pins (1/2) port 0 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 3 7-bit i/o port input/output mode can be specified in 1-bit units. n-ch open-drain i/o port an on-chip pull-up resistor can be specified by a mask option (mask rom version only). leds can be driven directly. an on-chip pull-up resistor can be used by setting software. port 6 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. 40 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud (1) port pins (2/2) pin name i/o function after reset alternate function p70 i/o input ti000/to00 p71 ti010 p72 ti50/to50 p73 ti51/to51 p74 ti011/pcl p75 ti001/to01/buz p80 i/o input ss1 (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si1 input serial interface serial data input input p20 si3 p34/t x d2 so1 output serial interface serial data output input p21 so3 p35/r x d2 sck1 i/o serial interface serial clock input/output input p22 sck3 p36/asck2 ss1 input serial interface chip select input input p80 r x d0 input asynchronous serial interface serial data input input p23 r x d2 p35/so3 t x d0 output asynchronous serial interface serial data output input p24 t x d2 p34/si3 asck0 input asynchronous serial interface serial clock input input p25 asck2 p36/sck3 ti000 input external count clock input to 16-bit timer/event counter 00. input p70/to00 capture trigger input to capture registers (cr000, cr010) of 16-bit timer/event counter 00 ti010 capture trigger input to capture register (cr000) of 16-bit p71 timer/event counter 00 ti001 external count clock input to 16-bit timer/event counter 01. p75/to01/buz capture trigger input to capture registers (cr001, cr011) of 16-bit timer/event counter 01 external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges) port 7 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 8 1-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. 41 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud (2) non-port pins (2/2) pin name i/o function after reset alternate function ti011 input capture trigger input to capture register (cr001) of 16-bit input p74/pcl timer/event counter 01 ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to00 output 16-bit timer/event counter 00 output input p70/ti000 to01 16-bit timer/event counter 01 output p75/ti001/buz to50 8-bit timer/event counter 50 output p72/ti50 to51 8-bit timer/event counter 51 output p73/ti51 pcl output clock output (for main system clock and subsystem clock input p74/ti011 trimming) buz output buzzer output input p75/ti001/to01 ad0 to ad7 i/o lower address/data bus when expanding external memory input p40 to p47 a8 to a15 output higher address bus when expanding external memory input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation from external memory p65 wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information input p67 output to ports 4 and 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input and analog power supply av ss a/d converter ground potential. connect to v ss0 or v ss1 . reset input system reset input input x1 input resonator connection for main system clock x2 xt1 input resonator connection for subsystem clock xt2 v dd0 positive power supply for ports v dd1 positive power supply (other than ports) v ss0 ground potential for ports v ss1 ground potential (other than ports) ic internally connected. connect directly to v ss0 or v ss1 . v pp flash memory programming mode setting. high-voltage application for program write/verify 42 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud 3.2 description of pin functions 3.2.1 p00 to p03 (port 0) p00 to p03 function as a 4-bit i/o port. besides serving as an i/o port, they also function as external interrupt inputs and an a/d converter external trigger input. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 4-bit i/o port. p00 to p03 can be specified as input or output in 1-bit units using port mode register 0 (pm0). on-chip pull-up resistors can be connected by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, these pins function as external interrupt request inputs and an a/d converter external trigger input. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins for which the valid edge can be specified (rising edge, falling edge, or both rising and falling edges). (b) adtrg a/d converter external trigger input pin. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by using bits 1 and 2 (ega00, ega01) of the a/d converter mode register (adm0) and set the interrupt mask flag (pmk3) to 1. 3.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit input-only port. besides serving as an input port, they also function as a/d converter analog inputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit input-only port. (2) control mode these pins function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see (4) ani0/p10 to ani7/p17 in 13.6 cautions for a/d converter . 3.2.3 p20 to p25 (port 2) p20 to p25 function as a 6-bit i/o port. besides serving as an i/o port, they function as data i/o and clock i/o for serial interfaces csi1 and uart0. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 6-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 2 (pm2). on-chip pull-up resistors can be connected by setting pull-up resistor option register 2 (pu2). 43 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud (2) control mode these pins function as data i/o and clock i/o for serial interfaces csi1 and uart0. (a) si1 serial data input pin for serial interface csi1. (b) so1 serial data output pin for serial interface csi1. (c) sck1 serial clock i/o pin for serial interface csi1. (d) r x d0 serial data input pin for serial interface uart0. (e) t x d0 serial data output pin for serial interface uart0. (f) asck0 serial clock input pin for serial interface uart0. 3.2.4 p30 to p36 (port 3) p30 to p36 function as a 7-bit i/o port. besides serving as an i/o port, they also function as data i/o and clock i/o for serial interfaces sio3 and uart2. p30 to p33 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 7-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 3 (pm3). p30 to p33 are n-ch open drain i/o pins. on-chip pull-up resistors can be connected via a mask option (mask rom version only). on-chip pull-up resistors can be connected to p34 to p36 by setting pull- up resistor option register 3 (pu3). (2) control mode these pins function as data i/o and clock i/o for serial interfaces sio3 and uart2. (a) si3 serial data input pin for serial interface sio3. (b) so3 serial data output pin for serial interface sio3. (c) sck3 serial clock i/o pin for serial interface sio3. (d) r x d2 serial data input pin for serial interface uart2. 44 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud (e) t x d2 serial data output pin for serial interface uart2. (f) asck2 serial clock input pin for serial interface uart2. 3.2.5 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. besides serving as an i/o port, they also function as an address/data bus. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating modes can be specified. caution when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. (1) port mode these pins function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 4 (pm4). on-chip pull-up resistors can be connected by setting pull-up resistor option register 4 (pu4). (2) control mode these ports function as the lower address/data bus pins (ad0 to ad7) in external memory expansion mode. 3.2.6 p50 to p57 (port 5) p50 to p57 function as an 8-bit i/o port. besides serving as an i/o port, they also function as an address bus. port 5 can drive leds directly. the following operating modes can be specified. (1) port mode these pins function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 5 (pm5). on-chip pull-up resistors can be connected by setting pull-up resistor option register 5 (pu5). (2) control mode these ports function as the higher address bus pins (a8 to a15) in external memory expansion mode. 3.2.7 p64 to p67 (port 6) p64 to p67 function as a 4-bit i/o port. besides serving as an i/o port, they are also used for control in external memory expansion mode. the following operating modes can be specified. (1) port mode these pins function as a 4-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 6 (pm6). on-chip pull-up resistors can be connected by setting pull-up resistor option register 6 (pu6). (2) control mode these pins function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. caution when external wait is not used in external memory expansion mode, p66 can be used as an i/o port. 45 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud 3.2.8 p70 to p75 (port 7) p70 to p75 function as a 6-bit i/o port. besides serving as an i/o port, they also function as timer i/o, clock output, and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 6-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 7 (pm7). on-chip pull-up resistors can be connected by setting pull-up resistor option register 7 (pu7). p70 and p71 are also capture trigger signal input pins of 16-bit timer/event counters 00 and 01 with a valid edge input. (2) control mode these pins function as timer i/o, clock output, and buzzer output. (a) ti000 external count clock input pin to 16-bit timer/event counter 00 and capture trigger signal input pin to the 16- bit timer/event counter 00 capture registers (cr000, cr010). (b) ti001 external count clock input pin to 16-bit timer/event counter 01 and capture trigger signal input pin to the 16- bit timer/event counter 01 capture registers (cr001, cr011). (c) ti010 capture trigger signal input pin to the 16-bit timer/event counter 00 capture register (cr000). (d) ti011 capture trigger signal input pin to the 16-bit timer/event counter 01 capture register (cr001). (e) ti50 and ti51 external count clock input pins to 8-bit timer/event counters 50 and 51. (f) to00, to01, to50, and to51 timer output pins. (g) pcl clock output pin. (h) buz buzzer output pin. 46 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud 3.2.9 p80 (port 8) p80 is a 1-bit i/o port. besides serving as an i/o port, it also functions as the chip select input of serial interface csi1. the following operating modes can be specified in 1-bit units. (1) port mode this pin functions as a 1-bit i/o port. it can be specified as input or output in 1-bit units using port mode register 8 (pm8). an on-chip pull-up resistor can be connected by setting pull-up resistor option register 8 (pu8). (2) control mode this pin functions as the chip select input pin (ss1) of serial interface csi1. 3.2.10 av ref this is the a/d converter reference voltage input pin. this pin is also used for the analog power supply. when using the a/d converter, supply power to this pin. when the a/d converter is not used, connect this pin directly to v ss0 or v ss1 . 3.2.11 av ss this is the ground potential pin of the a/d converter. use the same potential as that of the v ss0 pin or v ss1 pin even when not using the a/d converter. 3.2.12 reset this is an active-low system reset input pin. 3.2.13 x1 and x2 resonator connection pins for main system clock. for an external clock supply, input the clock signal to x1 and its inverted signal to x2. 3.2.14 xt1 and xt2 resonator connection pins for subsystem clock. for an external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 3.2.15 v dd0 and v dd1 v dd0 is the positive power supply pin for the ports. v dd1 is the positive power supply pin for other than the ports. 3.2.16 v ss0 and v ss1 v ss0 is the ground potential pin for the ports. v ss1 is the ground potential pin for other than the ports. 3.2.17 v pp (flash memory versions only) high-voltage application pin for flash memory programming mode setting and program write/verify. handle in either of the following ways. independently connect a 10 k ? pull-down resistor. set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in programming mode and directly to v ss0 or v ss1 in normal operation mode. 47 chapter 3 pin functions ( pd780078 subseries) user? manual u14260ej3v1ud as short as possible ic v ss0 or v ss1 when there is a potential difference between the v pp pin and v ss0 pin or v ss1 pin because the wiring between the two pins is too long or external noise is input to the v pp pin, the user program may not operate normally. 3.2.18 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780078 subseries at delivery. connect it directly to v ss0 or v ss1 with the shortest possible wiring in the normal operating mode. when there is a potential difference between the ic pin and v ss0 pin or v ss1 pin because the wiring between the two pins is too long or external noise is input to the ic pin, the user program may not operate normally. ? connect ic pin to v ss0 or v ss1 pin directly. 48 chapter 3 pin functions ( pd780078 subseries) user s manual u14260ej3v1ud 3.3 pin i/o circuits and recommended connection of unused pins table 3-1 shows the types of pin i/o circuits and the recommended connections of unused pins. refer to figure 3-1 for the configuration of the i/o circuit of each type. table 3-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 or v ss1 via a resistor. p03/intp3/adtrg output: leave open. p10/ani0 to p17/ani7 25 input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . p20/si1 8-c i/o input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 p21/so1 5-h via a resistor. p22/sck1 8-c output: leave open. p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input: connect directly to v ss0 or v ss1 . (for mask rom version) output: leave open at low-level output with the output latch p30, p31 13-p of the port set to 0. (for flash memory version) p32, p33 13-s (for mask rom version) p32, p33 13-r (for flash memory version) p34/si3/t x d2 8-c input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 p35/so3/r x d2 via a resistor. p36/sck3/asck2 output: leave open. p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 or v dd1 via a resistor. output: leave open. 49 chapter 3 pin functions ( pd780078 subseries) user s manual u14260ej3v1ud table 3-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p50/a8 to p57/a15 5-h i/o input: independently connect to v dd0 , v dd1 , v ss0 , or p64/rd v ss1 via a resistor. p65/wr output: leave open. p66/wait p67/astb p70/ti000/to00 8-c p71/ti010 p72/ti50/to50 p73/ti51/to51 p74/ti011/pcl p75/ti001/to01/buz p80/ss1 input: connect to v ss0 or v ss1 via a resistor. output: leave open. reset 2 input xt1 16 connect directly to v dd0 or v dd1 . xt2 leave open. av ref connect directly to v ss0 or v ss1 . av ss ic (for mask rom version) v pp independently connect a 10 k ? pull-down resistor or (for flash memory version) connect directly to v ss0 or v ss1 . 50 chapter 3 pin functions ( pd780078 subseries) user s manual u14260ej3v1ud figure 3-1. pin i/o circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pull-up enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable type 13-q data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? data output disable in/out n-ch data output disable in/out n-ch type 13-p input enable v ss0 input enable v ss0 type 13-r v ss0 v ss0 v ss0 51 chapter 3 pin functions ( pd780078 subseries) user s manual u14260ej3v1ud figure 3-1. pin i/o circuits (2/2) p-ch feedback cut-off xt1 xt2 type 13-s type 16 data output disable in/out n-ch input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 type 25 v ss0 in v dd0 mask option ? ? ? ? ? ? 52 user? manual u14260ej3v1ud chapter 4 pin functions ( pd780078y subseries) 4.1 pin function list (1) port pins (1/2) pin name i/o function after reset alternate function p00 i/o input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input-only port. p20 i/o input si1 p21 so1 p22 sck1 p23 rxd0 p24 txd0 p25 asck0 p30 i/o input p31 p32 sda0 p33 scl0 p34 si3/t x d2 p35 so3/r x d2 p36 sck3/asck2 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. p64 i/o input rd p65 wr p66 wait p67 astb port 0 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 3 7-bit i/o port input/output mode can be specified in 1-bit units. n-ch open-drain i/o port on-chip pull-up resistor can be specified by mask option (p30 and p31 are mask rom version only). leds can be driven directly. an on-chip pull-up resistor can be used by setting software. port 6 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. 53 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud (1) port pins (2/2) pin name i/o function after reset alternate function p70 i/o input ti000/to00 p71 ti010 p72 ti50/to50 p73 ti51/to51 p74 ti011/pcl p75 ti001/to01/buz p80 i/o input ss1 (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si1 input serial interface serial data input input p20 so1 output serial interface serial data output input p21 sda0 i/o serial interface serial data input/output input p32 sck1 i/o serial interface serial clock input/output input p22 sck3 p30/asck2 scl0 p33 ss1 input serial interface chip select input input p80 r x d0 input asynchronous serial interface serial data input input p23 r x d2 p35/so3 t x d0 output asynchronous serial interface serial data output input p24 t x d2 p34/si3 asck0 input asynchronous serial interface serial clock input input p25 asck2 p36/sck3 ti000 input external count clock input to 16-bit timer/event counter 00. input p70/to00 capture trigger input to capture registers (cr000, cr010) of 16-bit timer/event counter 00 ti010 capture trigger input to capture register (cr000) of 16-bit p71 timer/event counter 00 ti001 external count clock input to 16-bit timer/event counter 01. p75/to01/buz capture trigger input to capture registers (cr001, cr011) of 16-bit timer/event counter 01 port 7 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges) port 8 1-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. 54 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud (2) non-port pins (2/2) pin name i/o function after reset alternate function ti011 input capture trigger input to capture register (cr001) of 16-bit input p74/pcl timer/event counter 01 ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to00 output 16-bit timer/event counter 00 output input p70/ti000 to01 16-bit timer/event counter 01 output p75/ti001/buz to50 8-bit timer/event counter 50 output p72/ti50 to51 8-bit timer/event counter 51 output p73/ti51 pcl output clock output (for main system clock and subsystem clock input p74/ti011 trimming) buz output buzzer output input p75/ti001/to01 ad0 to ad7 i/o lower address/data bus when expanding external memory input p40 to p47 a8 to a15 output higher address bus when expanding external memory input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation from external memory p65 wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information input p67 output to ports 4 and 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input and analog power supply av ss a/d converter ground potential. connect to v ss0 or v ss1 . reset input system reset input input x1 input resonator connection for main system clock x2 xt1 input resonator connection for subsystem clock xt2 v dd0 positive power supply for ports v dd1 positive power supply (other than ports) v ss0 ground potential for ports v ss1 ground potential (other than ports) ic internally connected. connect directly to v ss0 or v ss1 . v pp flash memory programming mode setting. high-voltage application for program write/verify 55 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud 4.2 description of pin functions 4.2.1 p00 to p03 (port 0) p00 to p03 function as a 4-bit i/o port. besides serving as an i/o port, they also function as external interrupt inputs and an a/d converter external trigger input. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 4-bit i/o port. p00 to p03 can be specified as input or output in 1-bit units using port mode register 0 (pm0). on-chip pull-up resistors can be connected by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, these pins function as external interrupt request inputs and an a/d converter external trigger input. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins for which the valid edge can be specified (rising edge, falling edge, or both rising and falling edges). (b) adtrg a/d converter external trigger input pin. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by using bits 1 and 2 (ega00, ega01) of the a/d converter mode register (adm0) and set the interrupt mask flag (pmk3) to 1. 4.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit input-only port. besides serving as an input port, they also function as a/d converter analog inputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit input-only port. (2) control mode these pins function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see (4) ani0/p10 to ani7/p17 in 13.6 cautions for a/d converter . 4.2.3 p20 to p25 (port 2) p20 to p25 function as a 6-bit i/o port. besides serving as an i/o port, they function as data i/o and clock i/o for serial interfaces csi1 and uart0. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 6-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 2 (pm2). on-chip pull-up resistors can be connected by setting pull-up resistor option register 2 (pu2). 56 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud (2) control mode these pins function as data i/o and clock i/o for serial interfaces csi1 and uart0. (a) si1 serial data input pin for serial interface csi1. (b) so1 serial data output pin for serial interface csi1. (c) sck1 serial clock i/o pin for serial interface csi1. (d) r x d0 serial data input pin for serial interface uart0. (e) t x d0 serial data output pin for serial interface uart0. (f) asck0 serial clock input pin for serial interface uart0. 4.2.4 p30 to p36 (port 3) p30 to p36 function as a 7-bit i/o port. besides serving as an i/o port, they also function as data i/o and clock i/o for serial interfaces sio3 and uart2. p30 to p33 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 7-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 3 (pm3). p30 to p33 are n-ch open drain i/o pins. mask rom version can contain pull-up resistors in p30 and p31 with the mask option. on-chip pull-up resistors can be connected to p34 to p36 by setting pull- up resistor option register 3 (pu3). (2) control mode these pins function as data i/o and clock i/o for serial interfaces sio3 and uart2. (a) si3 serial data input pin for serial interface sio3. (b) so3 serial data output pin for serial interface sio3. (c) sck3 serial clock i/o pin for serial interface sio3. (d) r x d2 serial data input pin for serial interface uart2. 57 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud (e) t x d2 serial data output pin for serial interface uart2. (f) asck2 serial clock input pin for serial interface uart2. 4.2.5 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. besides serving as an i/o port, they also function as an address/data bus. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating modes can be specified. caution when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. (1) port mode these pins function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 4 (pm4). on-chip pull-up resistors can be connected by setting pull-up resistor option register 4 (pu4). (2) control mode these ports function as the lower address/data bus pins (ad0 to ad7) in external memory expansion mode. 4.2.6 p50 to p57 (port 5) p50 to p57 function as an 8-bit i/o port. besides serving as an i/o port, they also function as an address bus. port 5 can drive leds directly. the following operating modes can be specified. (1) port mode these pins function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 5 (pm5). on-chip pull-up resistors can be connected by setting pull-up resistor option register 5 (pu5). (2) control mode these ports function as the higher address bus pins (a8 to a15) in external memory expansion mode. 4.2.7 p64 to p67 (port 6) p64 to p67 function as a 4-bit i/o port. besides serving as an i/o port, they are also used for control in external memory expansion mode. the following operating modes can be specified. (1) port mode these pins function as a 4-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 6 (pm6). on-chip pull-up resistors can be connected by setting pull-up resistor option register 6 (pu6). (2) control mode these pins function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. caution when external wait is not used in external memory expansion mode, p66 can be used as an i/o port. 58 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud 4.2.8 p70 to p75 (port 7) p70 to p75 function as a 6-bit i/o port. besides serving as an i/o port, they also function as timer i/o, clock output, and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 6-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 7 (pm7). on-chip pull-up resistors can be connected by setting pull-up resistor option register 7 (pu7). p70 and p71 are also capture trigger signal input pins of 16-bit timer/event counters 00 and 01 with a valid edge input. (2) control mode these pins function as timer i/o, clock output, and buzzer output. (a) ti000 external count clock input pin to 16-bit timer/event counter 00 and capture trigger signal input pin to the 16- bit timer/event counter 00 capture registers (cr000, cr010). (b) ti001 external count clock input pin to 16-bit timer/event counter 01 and capture trigger signal input pin to the 16- bit timer/event counter 01 capture registers (cr001, cr011). (c) ti010 capture trigger signal input pin to the 16-bit timer/event counter 00 capture register (cr000). (d) ti011 capture trigger signal input pin to the 16-bit timer/event counter 01 capture register (cr001). (e) ti50 and ti51 external count clock input pins to 8-bit timer/event counters 50 and 51. (f) to00, to01, to50, and to51 timer output pins. (g) pcl clock output pin. (h) buz buzzer output pin. 59 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud 4.2.9 p80 (port 8) p80 is a 1-bit i/o port. besides serving as an i/o port, it also functions as the chip select input of serial interface csi1. the following operating modes can be specified in 1-bit units. (1) port mode this pin functions as a 1-bit i/o port. it can be specified as input or output in 1-bit units using port mode register 8 (pm8). an on-chip pull-up resistor can be connected by setting pull-up resistor option register 8 (pu8). (2) control mode this pin functions as the chip select input pin (ss1) of serial interface csi1. 4.2.10 av ref this is the a/d converter reference voltage input pin. this pin is also used for the analog power supply. when using the a/d converter, supply power to this pin. when the a/d converter is not used, connect this pin directly to v ss0 or v ss1 . 4.2.11 av ss this is the ground potential pin of the a/d converter. use the same potential as that of the v ss0 pin or v ss1 pin even when not using the a/d converter. 4.2.12 reset this is an active-low system reset input pin. 4.2.13 x1 and x2 resonator connection pins for main system clock. for an external clock supply, input the clock signal to x1 and its inverted signal to x2. 4.2.14 xt1 and xt2 resonator connection pins for subsystem clock. for an external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 4.2.15 v dd0 and v dd1 v dd0 is the positive power supply pin for the ports. v dd1 is the positive power supply pin for other than the ports. 4.2.16 v ss0 and v ss1 v ss0 is the ground potential pin for the ports. v ss1 is the ground potential pin for other than the ports. 4.2.17 v pp (flash memory versions only) high-voltage application pin for flash memory programming mode setting and program write/verify. handle in either of the following ways. independently connect a 10 k ? pull-down resistor. set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in programming mode and directly to v ss0 or v ss1 in normal operation mode. 60 chapter 4 pin functions ( pd780078y subseries) user? manual u14260ej3v1ud as short as possible ic v ss0 or v ss1 when there is a potential difference between the v pp pin and v ss0 pin or v ss1 pin because the wiring between the two pins is too long or external noise is input to the v pp pin, the user program may not operate normally. 4.2.18 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780078y subseries at delivery. connect it directly to v ss0 or v ss1 with the shortest possible wiring in the normal operating mode. when there is a potential difference between the ic pin and v ss0 pin or v ss1 pin because the wiring between the two pins is too long or external noise is input to the ic pin, the user program may not operate normally. ? connect ic pin to v ss0 or v ss1 pin directly. 61 chapter 4 pin functions ( pd780078y subseries) user s manual u14260ej3v1ud 4.3 pin i/o circuits and recommended connection of unused pins table 4-1 shows the types of pin i/o circuits and the recommended connections of unused pins. refer to figure 4-1 for the configuration of the i/o circuit of each type. table 4-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 or v ss1 via a resistor. p03/intp3/adtrg output: leave open. p10/ani0 to p17/ani7 25 input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . p20/si1 8-c i/o input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 p21/so1 5-h via a resistor. p22/sck1 8-c output: leave open. p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input: connect directly to v ss0 or v ss1 . (for mask rom version) output: leave open at low-level output with the output p30, p31 13-p latch of the port set to 0. (for flash memory version) p32/sda0 13-r p33/scl0 p34/si3/t x d2 8-c input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 p35/so3/r x d2 via a resistor. p36/sck3/asck2 output: leave open. p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 or v dd1 via a resistor. output: leave open. 62 chapter 4 pin functions ( pd780078y subseries) user s manual u14260ej3v1ud table 4-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p50/a8 to p57/a15 5-h i/o input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 p64/rd via a resistor. p65/wr output: leave open. p66/wait p67/astb p70/ti000/to00 8-c p71/ti010 p72/ti50/to50 p73/ti51/to51 p74/ti011/pcl p75/ti001/to01/buz p80/ss1 input: connect to v ss0 or v ss1 via a resistor. output: leave open. reset 2 input xt1 16 connect directly to v dd0 or v dd1 . xt2 leave open. av ref connect directly to v ss0 or v ss1 . av ss ic (for mask rom version) v pp independently connect a 10 k ? pull-down resistor or (for flash memory version) connect directly to v ss0 or v ss1 . 63 chapter 4 pin functions ( pd780078y subseries) user s manual u14260ej3v1ud figure 4-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pull-up enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable type 13-q data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? data output disable in/out n-ch data output disable in/out n-ch type 13-p input enable v ss0 input enable v ss0 type 13-r v ss0 v ss0 v ss0 p-ch feedback cut-off xt1 xt2 type 16 input enable comparator + p-ch n-ch v ref (threshold voltage) type 25 v ss0 in 64 user? manual u14260ej3v1ud chapter 5 cpu architecture 5.1 memory spaces products in the pd780078, 780078y subseries can each access a 64 kb memory space. figures 5-1 to 5-3 show the memory maps. caution the initial value of the memory size switching register (ims) and internal expansion ram size switching register (ixs) of all products ( pd780078, 780078y subseries) is fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. value of ims value of ixs pd780076, 780076y cch 0ah pd780078, 780078y cfh pd78f0078, 78f0078y value corresponding to mask rom version figure 5-1. memory map ( pd780076, 780076y) special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits reserved general-purpose registers 32 8 bits internal expansion ram 1024 8 bits external memory 13312 8 bits internal rom 49152 8 bits rom/ram space in which instructions can be fetched data memory space vector table area callt table area program area callf entry area program area ffffh ff00h feffh f800h f7ffh 1000h 0fffh 0800h 07ffh 0040h 003fh 0080h 007fh 0000h bfffh c000h bfffh f400h f3ffh 0000h fee0h fedfh fb00h faffh 65 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-2. memory map ( pd780078, 780078y) special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits reserved general-purpose registers 32 8 bits internal expansion ram 1024 8 bits external memory 1024 8 bits internal rom 61440 8 bits data memory space vector table area callt table area program area callf entry area program area ffffh ff00h feffh f800h f7ffh 1000h 0fffh 0800h 07ffh 0040h 003fh 0080h 007fh 0000h efffh f000h efffh f400h f3ffh 0000h fee0h fedfh fb00h faffh rom/ram space in which instructions can be fetched 66 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-3. memory map ( pd78f0078, 78f0078y) special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits reserved general-purpose registers 32 8 bits internal expansion ram 1024 8 bits external memory 1024 8 bits flash memory 61440 8 bits data memory space vector table area callt table area program area callf entry area program area ffffh ff00h feffh f800h f7ffh 1000h 0fffh 0800h 07ffh 0040h 003fh 0080h 007fh 0000h efffh f000h efffh f400h f3ffh 0000h fee0h fedfh fb00h faffh rom/ram space in which instructions can be fetched 67 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.1.1 internal program memory space the internal program memory space contains the program and table data. normally, it is addressed with the program counter (pc). the pd780078, 780078y subseries incorporate internal rom (mask rom or flash memory), as listed below. table 5-1. internal memory capacity part number type capacity pd780076, 780076y mask rom 49152 8 bits (0000h to bfffh) pd780078, 780078y 61440 8 bits (0000h to efffh) pd78f0078, 78f0078y flash memory 61440 8 bits (0000h to efffh) the internal program memory space is divided into the following three areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the program start addresses for branch upon reset input or interrupt request generation are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 5-2. vector table vector table address interrupt source 0000h reset input 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intser0 0010h intsr0 0012h intst0 0014h intcsi1 0016h intcsi3 0018h intiic0 note 001ah intwti vector table address interrupt source 001ch inttm000 001eh inttm010 0020h inttm50 0022h inttm51 0024h intad0 0026h intwt 0028h intkr 002ah intser2 002ch intsr2 002eh intst2 0030h inttm001 0032h inttm011 003eh brk note pd780078y subseries only (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 68 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.1.2 internal data memory space the pd780078, 780078y subseries incorporate the following on-chip high-speed rams. (1) internal high-speed ram the 1024-byte area fb00h to feffh is allocated to the internal high-speed ram. the 32-byte area fee0h to feffh is allocated to four general-purpose register banks composed of eight 8-bit registers. this area cannot be used as a program area in which instructions are written for execution. the internal high-speed ram can also be used as a stack memory. (2) internal expansion ram the 1024-byte area f400h to f7ffh is allocated to the internal expansion ram. like the internal high-speed ram, the internal expansion ram can be used as a normal data area, but it can also be used as a program area in which instructions are written for execution. the internal expansion ram cannot be used as a stack memory. 5.1.3 special function register (sfr) area on-chip peripheral hardware special function registers (sfr) are allocated in the area ff00h to ffffh (refer to 5.2.3 special function registers (sfr) and table 5-3 special function register list ). caution do not access addresses where an sfr is not assigned. 5.1.4 external memory space the external memory space is accessible using the memory expansion mode register (mem). external memory space can store program, table data, etc., and allocate peripheral devices. 69 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.1.5 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memory relevant to the execution of instructions for the pd780078, 780078y subseries, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 5-4 to 5-6 show the correspondence between data memory and addressing. for details of each addressing mode, see 5.4 operand address addressing . figure 5-4. correspondence between data memory and addressing ( pd780076, 780076y) 0000h general-purpose registers 32 8 bits internal rom 49152 8 bits external memory 13312 8 bits c000h bfffh f400h f3ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh internal expansion ram 1024 8 bits 70 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-5. correspondence between data memory and addressing ( pd780078, 780078y) 0000h general-purpose registers 32 8 bits internal rom 61440 8 bits external memory 1024 8 bits f000h efffh f400h f3ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh internal expansion ram 1024 8 bits 71 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-6. correspondence between data memory and addressing ( pd78f0078, 78f0078y) 0000h general-purpose registers 32 8 bits flash memory 61440 8 bits external memory 1024 8 bits f000h efffh f400h f3ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh internal expansion ram 1024 8 bits 72 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.2 processor registers the pd780078, 780078y subseries incorporate the following processor registers. 5.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-7. program counter format 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 5-8. program status word format 70 psw ie z rbs1 ac rbs0 0 isp cy 73 chapter 5 cpu architecture user s manual u14260ej3v1ud (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledgment operations of the cpu. when ie is 0 the interrupt disabled (di) state is set, and only non-maskable interrupt requests become acknowledgeable. other interrupt requests are all disabled. when ie is 1 the interrupt enabled (ei) state is set and interrupt request acknowledgment enable is controlled by the in-service priority flag (isp), the interrupt mask flag corresponding to each interrupt source and the priority specification flag. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags used to select one of the four register banks. the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored in these flags. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by the priority specification flag register (pr0l, pr0h, pr1l) (refer to 19.3 (3) priority specification flag registers (pr0l, pr0h, pr1l) ) are disabled for acknowledgment. actual interrupt request acknowledgment is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores an overflow or underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register used to hold the start address of the memory stack area. only the internal high-speed ram area (fb00h to feffh) can be set as the stack area. 74 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-9. stack pointer format 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 5-10 and 5-11. caution since reset input makes the sp contents undefined, be sure to initialize the sp before using the stack memory. figure 5-10. data to be saved to stack memory (a) push rp instruction (when sp is fee0h) (b) call, callf, callt instructions (when sp is fee0h) (c) interrupt, brk instruction (when sp is fee0h) fee0h register pair upper register pair lower fedeh sp sp fee0h fedfh fedeh fee0h fee0h fedfh fedeh pc15 to pc8 pc7 to pc0 fedeh sp sp fee0h fee0h fedfh fedeh psw pc15 to pc8 feddh sp sp feddh pc7 to pc0 75 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-11. data to be restored from stack memory (a) pop rp instruction (when sp is fedeh) (b) ret instruction (when sp is fedeh) (c) reti, retb instructions (when sp is feddh) 5.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (fee0h to feffh) of the data memory. they consist of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit registers can also be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. fee0h register pair upper register pair lower fedeh sp sp fee0h fedfh fedeh fee0h fee0h fedfh fedeh pc15 to pc8 pc7 to pc0 fedeh sp sp fee0h fee0h fedfh fedeh psw pc15 to pc8 feddh sp sp feddh pc7 to pc0 76 chapter 5 cpu architecture user s manual u14260ej3v1ud figure 5-12. general-purpose register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h 77 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.2.3 special function registers (sfr) unlike a general-purpose register, each special function register has a special function. they are allocated in the area ff00h to ffffh. the special function registers can be manipulated like the general-purpose registers, with operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describe the symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describe the symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describe the symbol reserved by assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 5-3 gives a list of the special function registers. the meanings of items in the table are as follows. symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. when using the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. r/w indicates whether the corresponding special function register can be read or written. r/w: read/write r: read only w: write only manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). indicates a bit unit for which manipulation is not possible. after reset indicates each register status upon reset input. 78 chapter 5 cpu architecture user s manual u14260ej3v1ud table 5-3. special function register list (1/3) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff00h port register 0 p0 r/w ? 00h ff01h port register 1 p1 r ? undefined ff02h port register 2 p2 r/w ? 00h ff03h port register 3 p3 ? ff04h port register 4 p4 ? ff05h port register 5 p5 ? ff06h port register 6 p6 ? ff07h port register 7 p7 ? ff08h port register 8 p8 ? ff0ah 16-bit timer capture/compare register 000 cr000 undefined ff0bh ff0ch 16-bit timer capture/compare register 010 cr010 ff0dh ff0eh 16-bit timer counter 00 tm00 r 0000h ff0fh ff10h 8-bit timer compare register 50 cr50 r/w undefined ff11h 8-bit timer compare register 51 cr51 ff12h 8-bit timer counter 50 tm5 tm50 r ? 00h ff13h 8-bit timer counter 51 tm51 ff14h transmit buffer register 2 txb2 r/w ffh ff15h receive buffer register 2 rxb2 r ffh ff16h a/d conversion result register 0 adcr0 0000h ff17h ff18h transmit shift register 0 txs0 w ffh receive buffer register 0 rxb0 r ff19h transmit buffer register 1 sotb1 r/w undefined ff1ah serial i/o shift register 1 sio1 r ff1bh serial i/o shift register 3 sio3 r/w ff1fh iic shift register 0 note iic0 00h ff20h port mode register 0 pm0 ? ffh ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff24h port mode register 4 pm4 ? ff25h port mode register 5 pm5 ? ff26h port mode register 6 pm6 ? ff27h port mode register 7 pm7 ? ff28h port mode register 8 pm8 ? note pd780078y subseries only 79 chapter 5 cpu architecture user s manual u14260ej3v1ud table 5-3. special function register list (2/3) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff32h pull-up resistor option register 2 pu2 ? ff33h pull-up resistor option register 3 pu3 ? ff34h pull-up resistor option register 4 pu4 ? ff35h pull-up resistor option register 5 pu5 ? ff36h pull-up resistor option register 6 pu6 ? ff37h pull-up resistor option register 7 pu7 ? ff38h pull-up resistor option register 8 pu8 ? ff40h clock output select register cks ? ff41h watch timer operation mode register wtm ? ff42h watchdog timer clock select register wdcs ff47h memory expansion mode register mem ? ff48h external interrupt rising edge enable register egp ? ff49h external interrupt falling edge enable register egn ? ff60h 16-bit timer mode control register 00 tmc00 ? ff61h prescaler mode register 00 prm00 ff62h capture/compare control register 00 crc00 ? ff63h 16-bit timer output control register 00 toc00 ? ff64h 16-bit timer mode control register 01 tmc01 ? ff65h prescaler mode register 01 prm01 ff66h capture/compare control register 01 crc01 ? ff67h 16-bit timer output control register 01 toc01 ? ff68h 16-bit timer capture/compare register 001 cr001 undefined ff69h ff6ah 16-bit timer capture/compare register 011 cr011 ff6bh ff6ch 16-bit timer counter 01 tm01 r 0000h ff6dh ff70h 8-bit timer mode control register 50 tmc50 r/w ? 00h ff71h timer clock select register 50 tcl50 ff78h 8-bit timer mode control register 51 tmc51 ? ff79h timer clock select register 51 tcl51 ff80h a/d converter mode register 0 adm0 ? ff81h analog input channel specification register 0 ads0 ff90h asynchronous serial interface mode register 2 asim2 ? ff91h transfer mode specification register 2 trmc2 ? 02h ff92h clock select register 2 cksel2 00h ff93h baud rate generator control register 2 brgc2 80 chapter 5 cpu architecture user s manual u14260ej3v1ud table 5-3. special function register list (3/3) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff94h asynchronous serial interface status register 2 asis2 r 00h ff95h asynchronous serial interface transmit status register 2 asif2 ffa0h asynchronous serial interface mode register 0 asim0 r/w ? ffa1h asynchronous serial interface status register 0 asis0 r ffa2h baud rate generator control register 0 brgc0 r/w ffa8h iic control register 0 note 1 iicc0 ? ffa9h iic status register 0 note 1 iics0 r ? ffaah iic transfer clock select register 0 note 1 iiccl0 r/w ? ffabh slave address register 0 note 1 sva0 ffb0h serial operation mode register 1 csim1 ? ffb1h serial clock select register 1 csic1 ? 10h ffb8h serial operation mode register 3 csim3 ? 00h ffe0h interrupt request flag register 0l if0 if0l ?? ffe1h interrupt request flag register 0h if0h ? ffe2h interrupt request flag register 1l if1l ? ffe4h interrupt mask flag register 0l mk0 mk0l ?? ffh ffe5h interrupt mask flag register 0h mk0h ? ffe6h interrupt mask flag register 1l mk1l ? ffe8h priority level specification flag register 0l pr0 pr0l ?? ffe9h priority level specification flag register 0h pr0h ? ffeah priority level specification flag register 1l pr1l ? fff0h memory size switching register ims cfh note 2 fff4h internal expansion ram size switching register ixs 0ch note 3 fff8h memory expansion wait setting register mm ? 10h fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time select register osts 04h fffbh processor clock control register pcc ? notes 1. pd780078y subseries only 2. although the default value of this register is cfh, set the value corresponding to each product as indicated below. pd780076, 780076y: cch pd780078, 780078y: cfh pd78f0078, 78f0078y: value for mask rom version 3. although the default value of this register is 0ch, initialize this register to 0ah. 81 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 series instructions user? manual (u12326e) ). 5.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two s complement data ( 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relative branching from the start address of the following instruction to the 128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... 82 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 8 11 10 00001 643 callf fa 7 0 83 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 0 operation code 84 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 85 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 implied addressing [function] the register which functions as an accumulator (a, ax) in the general-purpose register area is automatically (implicitly) addressed. of the pd780078, 780078y subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu register a for multiplicand and register ax for product storage divuw register ax for dividend and quotient storage adjba/adjbs register a for storage of numeric values which become decimal correction targets ror4/rol4 register a for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of register a and register x is stored in ax. in this example, the a and ax registers are specified by implied addressing. 86 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.2 register addressing [function] the general-purpose register to be specified is accessed as an operand with the register specify code (rn and rpn) of an instruction word in the registered bank specified by the register bank select flags (rbs0 and rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code 87 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 opcode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (higher) opcode 88 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] below. [operand format] identifier description saddr label or immediate data indicating fe20h to ff1fh saddrp label or immediate data indicating fe20h to ff1fh (even address only) [description example] mov 0fe30h, a; when transferring the value in register a to saddr (fe30h) operation code 11110010 opcode 00110000 30h (saddr-offset) [illustration] when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 opcode saddr-offset 89 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.5 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 opcode 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 opcode sfr-offset 1 90 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.6 register indirect addressing [function] register pair contents specified with a register pair specify code in an instruction word of the register bank specified by the register bank select flags (rbs0 and rbs1) serve as an operand address for addressing the memory to be manipulated. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de 91 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified by the register bank select flags (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] hl 16 0 8 7 hl a 70 70 memory the contents of the addressed memory is transferred. +10 92 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.8 based indexed addressing [function] the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified by the register bank select flags (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] (selecting the b register) operation code 10101011 [illustration] hl 16 0 8 7 hl a 70 70 memory 70 + b ? ? ? ? ? the contents of the addressed memory is transferred. 93 chapter 5 cpu architecture user s manual u14260ej3v1ud 5.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing can be used to address the internal high-speed ram area only. [description example] in the case of push de (saving the de register) operation code 10110101 [illustration] fee0h fee0h fedfh fedeh d e fedeh sp sp 7 0 memory 94 user? manual u14260ej3v1ud chapter 6 port functions 6.1 port functions the pd780078, 780078y subseries incorporate eight input ports and 44 i/o ports. figure 6-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware i/o pins. figure 6-1. port types ? ? ? ? ? port 0 p00 ? ? ? ? ? ? ? ? ? port 1 p10 p17 ? ? ? ? ? ? ? port 2 p20 p25 ? ? ? ? ? ? ? port 3 p30 p36 ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 6 port 5 p50 p57 p64 p67 ? ? ? ? ? ? ? port 7 p70 p75 ? ? ? ? ? ? ? ? ? port 4 p40 p47 p03 port 8 p80 95 chapter 6 port functions user s manual u14260ej3v1ud table 6-1. port functions ( pd780078 subseries) pin name p00 p01 p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p70 p71 p72 p73 p74 p75 p80 function port 0 4-bit i/o port. input/output mode can be specified in 1-bit units . an on-chip pull-up resistor can be used by setting software. port 1 8-bit input-only port. port 2 6-bit i/o port. input/output mode can be specified in 1-bit units . an on-chip pull-up resistor can be used by setting software. port 3 n-ch open-drain i/o port. 7-bit i/o port. an on-chip pull-up resistor can be specified by a input/output mode can be specified mask option (mask rom version only). in 1-bit units. leds can be driven directly. an on-chip pull-up resistor can be used by setting software. port 4 8-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit i/o port. leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 6 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 7 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 8 1-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani7 si1 so1 sck1 rxd0 txd0 asck0 si3/t x d2 so3/r x d2 sck3/asck2 ad0 to ad7 a8 to a15 rd wr wait astb ti000/to00 ti010 ti50/to50 ti51/to51 ti011/pcl ti001/to01/buz ss1 96 chapter 6 port functions user s manual u14260ej3v1ud table 6-2. port functions ( pd780078y subseries) alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani7 si1 so1 sck1 rxd0 txd0 asck0 sda0 scl0 si3/t x d2 so3/r x d2 sck3/asck2 ad0 to ad7 a8 to a15 rd wr wait astb ti000/to00 ti010 ti50/to50 ti51/to51 ti011/pcl ti001/to01/buz ss1 pin name p00 p01 p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p70 p71 p72 p73 p74 p75 p80 function port 0 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 1 8-bit input-only port. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 3 n-ch open-drain i/o port. 7-bit i/o port. an on-chip pull-up resistor can be specified by a input/output mode can be specified mask opti on (p30 and p31 are mask rom version in 1-bit units. only). leds can be driven directly. an on-chip pull-up resistor can be used by setting software. port 4 8-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit i/o port. leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 6 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 7 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. port 8 1-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by setting software. 97 chapter 6 port functions user s manual u14260ej3v1ud 6.2 port configuration a port consists of the following hardware. table 6-3. port configuration item configuration control registers port mode register (pmm: m = 0, 2 to 8) port register (pm: m = 0 to 8) pull-up resistor option register (pum: m = 0, 2 to 8) ports total: 52 ports (8 inputs, 44 i/o) pull-up resistor mask rom version total: 44 (software control: 40, mask option: 4 note ) flash memory version total: 40 note two for the pd780078y subseries. 6.2.1 port 0 port 0 is a 4-bit i/o port with an output latch. port 0 can be set to the input or output mode in 1-bit units using port mode register 0 (pm0). an on-chip pull-up resistor can be connected to p00 to p03 in 1-bit units using pull-up resistor option register 0 (pu0). this port can also be used for external interrupt request input and a/d converter external trigger input. reset input sets port 0 to input mode. figure 6-2 shows a block diagram of port 0. cautions 1. port 0 functions alternately as an external interrupt request input pin. if the output mode of the port function is specified and the output level of the port is changed while interrupts are not disabled by the external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn), the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. 2. when the external interrupt request function is switched to the port function, edge detection may be performed. therefore, set bit n (egpn) of egp and bit n (egnn) of egn to 0 before selecting the port mode. 3. when using p03/intp3/adtrg as an a/d converter external trigger input, specify valid edges by setting bits 1 and 2 (ega00 and ega01) of a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1. remark n = 0 to 3 98 chapter 6 port functions user s manual u14260ej3v1ud figure 6-2. block diagram of p00 to p03 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal v dd0 p-ch p00/intp0 p02/intp2, p03/intp3/adtrg wr pu rd wr port wr pm pu00 to pu03 alternate function output latch (p00 to p03) pm00 to pm03 internal bus selector pu0 pm0 99 chapter 6 port functions user s manual u14260ej3v1ud 6.2.2 port 1 port 1 is an 8-bit input-only port. this port can also be used for a/d converter analog input. figure 6-3 shows a block diagram of port 1. figure 6-3. block diagram of p10 to p17 rd: read signal rd p10/ani0 to p17/ani7 a/d converter internal bus 100 chapter 6 port functions user s manual u14260ej3v1ud 6.2.3 port 2 port 2 is a 6-bit i/o port with an output latch. port 2 can be set to the input or output mode in 1-bit units using port mode register 2 (pm2). an on-chip pull-up resistor can be connected to p20 to p25 in 1-bit units using pull-up resistor option register 2 (pu2). this port can also be used for serial interface data i/o and clock i/o. reset input sets port 2 to input mode. figures 6-4 to 6-7 show block diagrams of port 2. caution when using p22/sck1 as a general-purpose port, set bit 4 (ckp1) of serial clock select register 1 (csic1) to 1. figure 6-4. block diagram of p20, p23, and p25 pu2: pull-up resistor option register 2 pm2: port mode register 2 rd: read signal wr : write signal v dd0 p-ch p20/si1, p23/rxd0, p25/asck0 wr pu rd wr port wr pm pu20, pu23, pu25 alternate function output latch (p20, p23, p25) pm20, pm23, pm25 internal bus selector pu2 pm2 101 chapter 6 port functions user s manual u14260ej3v1ud figure 6-5. block diagram of p21 pu2: pull-up resistor option register 2 pm2: port mode register 2 rd: read signal wr : write signal ss1: 3-wire sio chip select signal caution p21/so1 has a function to forcibly turn off the output buffer via ss1 (3-wire sio chip select signal). internal bus p21/so1 wr pu rd wr port wr pm pu21 output latch (p21) pm21 ss1 alternate function v dd0 p-ch selector pu2 pm2 102 chapter 6 port functions user s manual u14260ej3v1ud figure 6-6. block diagram of p22 pu2: pull-up resistor option register 2 pm2: port mode register 2 rd: read signal wr : write signal p22/sck1 wr pu rd wr port wr pm pu22 output latch (p22) pm22 alternate function alternate function v dd0 p-ch internal bus selector pu2 pm2 103 chapter 6 port functions user s manual u14260ej3v1ud figure 6-7. block diagram of p24 pu2: pull-up resistor option register 2 pm2: port mode register 2 rd: read signal wr : write signal p24/txd0 wr pu rd wr port wr pm pu24 output latch (p24) pm24 alternate function v dd0 p-ch internal bus selector pu2 pm2 104 chapter 6 port functions user s manual u14260ej3v1ud 6.2.4 port 3 ( pd780078 subseries) port 3 is a 7-bit i/o port with an output latch. port 3 can be set to the input or output mode in 1-bit units using port mode register 3 (pm3). this port has the following functions related to pull-up resistors. these functions differ depending on the port s higher 3 bits/lower 4 bits, and whether the product is a mask rom version or a flash memory version. table 6-4. pull-up resistor of port 3 ( pd780078 subseries) higher 3 bits (p34 to p36 pins) lower 4 bits (p30 to p33 pins) mask rom version an on-chip pull-up resistor can be an on-chip pull-up resistor can be specified connected in 1-bit units by pu3 in 1-bit units by a mask option flash memory version an on-chip pull-up resistor is not provided pu3: pull-up resistor option register 3 the p30 to p33 pins can drive leds directly. the p34 to p36 pins can also be used for serial interface data i/o and clock i/o. reset input sets port 3 to input mode. figures 6-8 to 6-10 show block diagrams of port 3. figure 6-8. block diagram of p30 and p31 ( pd780078 subseries) pm3: port mode register 3 rd: read signal wr : write signal rd pm30, pm31 p30, p31 n-ch wr port output latch (p30, p31) wr pm v dd0 selector internal bus mask option resistor ? ? ? ? ? ? ? ? ? ? mask rom version only no pull-up resistor for flash memory version pm3 105 chapter 6 port functions user s manual u14260ej3v1ud figure 6-9. block diagram of p32 and p33 ( pd780078 subseries) pm3: port mode register 3 rd: read signal wr : write signal rd pm32, pm33 p32, p33 n-ch wr port wr pm v dd0 output latch (p32, p33) selector internal bus mask option resistor ? ? ? ? ? ? ? ? ? ? mask rom version only no pull-up resistor for flash memory version pm3 106 chapter 6 port functions user s manual u14260ej3v1ud figure 6-10. block diagram of p34 to p36 ( pd780078 subseries) pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal v dd0 p-ch p34/si3/txd2, p35/so3/rxd2, p36/sck3/asck2 wr pu rd wr port wr pm pu34 to pu36 alternate function output latch (p34 to p36) pm34 to pm36 alternate function selector internal bus pu3 pm3 107 chapter 6 port functions user s manual u14260ej3v1ud 6.2.5 port 3 ( pd780078y subseries) port 3 is a 7-bit i/o port with an output latch. port 3 can be set to the input or output mode in 1-bit units using port mode register 3 (pm3). this port has the following functions related to pull-up resistors. these functions differ depending on the bit location and whether the product is a mask rom version or a flash memory version. table 6-5. pull-up resistor of port 3 ( pd780078y subseries) p34 to p36 pins p30 and p31 pins mask rom version an on-chip pull-up resistor can an on-chip pull-up resistor can be specified be connected in 1-bit units by in 1-bit units by mask option flash memory version pu3 an on-chip pull-up resistor is not provided pu3: pull-up resistor option register 3 caution the p32 and p33 pins have no pull-up resistor. the p30 to p33 pins can drive leds directly. the p32 to p36 pins can also be used for serial interface data i/o and clock i/o. reset input sets port 3 to input mode. figures 6-11 to 6-13 show block diagrams of port 3. figure 6-11. block diagram of p30 and p31 ( pd780078y subseries) pm3: port mode register 3 rd: read signal wr : write signal rd pm30, pm31 p30, p31 n-ch wr port wr pm v dd0 output latch (p30, p31) selector internal bus mask option resistor ? ? ? ? ? mask rom version only no pull-up resistor for flash memory version ? ? ? ? ? pm3 108 chapter 6 port functions user s manual u14260ej3v1ud figure 6-12. block diagram of p32 and p33 ( pd780078y subseries) pm3: port mode register 3 rd: read signal wr : write signal rd pm32, pm33 alternate function p32/sda0, p33/scl0 n-ch wr port output latch (p32, p33) wr pm internal bus selector pm3 109 chapter 6 port functions user s manual u14260ej3v1ud figure 6-13. block diagram of p34 to p36 ( pd780078y subseries) pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal v dd0 p-ch p34/si3/txd2, p35/so3/rxd2, p36/sck3/asck2 wr pu rd wr port wr pm pu34 to pu36 output latch (p34 to p36) pm34 to pm36 alternate function alternate function internal bus selector pu3 pm3 110 chapter 6 port functions user s manual u14260ej3v1ud 6.2.6 port 4 port 4 is an 8-bit i/o port with an output latch. port 4 can be set to the input or output mode in 1-bit units using port mode register 4 (pm4). an on-chip pull-up resistor can be connected to p40 to p47 in 1-bit units using pull-up resistor option register 4 (pu4). the interrupt request flag (krif) can be set to 1 by detecting falling edges. this port can also be used as an address/data bus in external memory expansion mode. reset input sets port 4 to input mode. figures 6-14 and 6-15 show a block diagram of port 4 and a block diagram of the falling edge detector, respectively. cautions 1. an on-chip pull-up resistor is not disconnected even if the external memory expansion mode is set when pu4n = 1 (n = 0 to 7). 2. when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. figure 6-14. block diagram of p40 to p47 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal internal bus rd p40/ad0 to p47/ad7 p-ch wr pu wr port wr pm pu40 to pu47 alternate function selector v dd0 output latch (p40 to p47) pm40 to pm47 alternate function selector memory expansion mode register (mem) pm4 pu4 111 chapter 6 port functions user s manual u14260ej3v1ud figure 6-15. block diagram of falling edge detector p40 p41 p42 p43 p44 p45 p46 p47 intkr falling edge detector 1 when mem = 01h 112 chapter 6 port functions user s manual u14260ej3v1ud 6.2.7 port 5 port 5 is an 8-bit i/o port with an output latch. port 5 can be set to the input or output mode in 1-bit units using port mode register 5 (pm5). an on-chip pull-up resistor can be connected to p50 to p57 in 1-bit units using pull-up resistor option register 5 (pu5). port 5 can drive leds directly. this port can also be used as an address bus in external memory expansion mode. reset input sets port 5 to input mode. figure 6-16 shows a block diagram of port 5. caution an on-chip pull-up resistor is not disconnected even if the external memory expansion mode is set when pu5n = 1 (n = 0 to 7). figure 6-16. block diagram of p50 to p57 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal internal bus rd p50/a8 to p57/a15 p-ch wr pu wr port wr pm pu50 to pu57 v dd0 selector output latch (p50 to p57) pm50 to pm57 alternate function selector pm5 memory expansion mode register (mem) pu5 113 chapter 6 port functions user s manual u14260ej3v1ud 6.2.8 port 6 port 6 is a 4-bit i/o port with an output latch. port 6 can be set to the input or output mode in 1-bit units using port mode register 6 (pm6). an on-chip pull-up resistor can be connected to p64 to p67 in 1-bit units using pull-up resistor option register 6 (pu6). this port can also be used for control signal output in external memory expansion mode. reset input sets port 6 to input mode. figures 6-17 and 6-18 show block diagrams of port 6. cautions 1. an on-chip pull-up resistor is not disconnected even if the external memory expansion mode is set when pu6n = 1 (n = 4 to 7). 2. when external wait is not used in external memory expansion mode, p66 can be used as an i/o port. figure 6-17. block diagram of p64, p65, and p67 pu6: pull-up resistor option register 6 pm6: port mode register 6 rd: read signal wr : write signal internal bus rd p64/rd, p65/wr, p67/astb p-ch wr pu wr port wr pm pu64, pu65, pu67 v dd0 selector output latch (p64, p65, p67) pm64, pm65, pm67 alternate function selector pm6 memory expansion mode register (mem) pu6 114 chapter 6 port functions user s manual u14260ej3v1ud figure 6-18. block diagram of p66 pu6: pull-up resistor option register 6 pm6: port mode register 6 rd: read signal wr : write signal internal bus rd p66/wait p-ch wr pu wr port wr pm pu66 pm66 v dd0 output latch (p66) alternate function selector selector memory expansion mode register (mem) pu6 pm6 115 chapter 6 port functions user s manual u14260ej3v1ud 6.2.9 port 7 port 7 is a 6-bit i/o port with an output latch. port 7 can be set to the input or output mode in 1-bit units using port mode register 7 (pm7). an on-chip pull-up resistor can be connected to p70 to p75 in 1-bit units using pull-up resistor option register 7 (pu7). this port can also be used for timer i/o, clock output, and buzzer output. reset input sets port 7 to input mode. figures 6-19 and 6-20 show block diagrams of port 7. figure 6-19. block diagram of p70 and p72 to p75 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal v dd0 p-ch p70/ti000/to00, p72/ti50/to50, p73/ti51/to51, p74/ti011/pcl, p75/ti001/to01/buz wr pu rd wr port wr pm pu70, pu72 to pu75 alternate function alternate function output latch (p70, p72 to p75) pm70, pm72 to pm75 internal bus selector pu7 pm7 116 chapter 6 port functions user s manual u14260ej3v1ud figure 6-20. block diagram of p71 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal v dd0 p-ch p71/ti010 wr pu rd wr port wr pm pu71 pm71 output latch (p71) alternate function internal bus selector pu7 pm7 117 chapter 6 port functions user s manual u14260ej3v1ud 6.2.10 port 8 port 8 is a 1-bit i/o port with an output latch. port 8 can be set to the input or output mode in 1-bit units using port mode register 8 (pm8). an on-chip pull-up resistor can be connected to p80 in 1-bit units using pull-up resistor option register 8 (pu8). this port can also be used for serial interface chip select input. reset input sets port 8 to input mode. figure 6-21 shows a block diagram of port 8. figure 6-21. block diagram of p80 pu8: pull-up resistor option register 8 pm8: port mode register 8 rd: read signal wr : write signal v dd0 p-ch p80/ss1 wr pu rd wr port wr pm pu80 pm80 output latch (p80) alternate function internal bus selector pu8 pm8 118 chapter 6 port functions user s manual u14260ej3v1ud 6.3 port function control registers the following three types of registers control the ports. port mode registers (pm0, pm2 to pm8) port registers (p0 to p8) pull-up resistor option registers (pu0, pu2 to pu8) (1) port mode registers (pm0, pm2 to pm8) these registers are used to set port input/output in 1-bit units. pm0 and pm2 to pm8 are independently set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 and pm2 to pm8 to ffh. when using a port pin as its alternate-function pin, set the port mode registers and output latches as shown in table 6-6. cautions 1. pins p10 and p17 are input-only pins. 2. port 0 functions alternately as an external interrupt request input pin. if the output mode of the port function is specified and the output level of the port is changed while interrupts are not disabled by the external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn), the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. if a port has an alternate function pin and it is used as an alternate output function, set the corresponding output latches (p0 and p2 to p8) to 0. 119 chapter 6 port functions user s manual u14260ej3v1ud figure 6-22. format of port mode register (pm0, pm2 to pm8) address: ff20h after reset: ffh r/w symbol 76543210 pm0 1111 pm03 pm02 pm01 pm00 address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 address: ff24h after reset: ffh r/w symbol 76543210 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 address: ff25h after reset: ffh r/w symbol 76543210 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 address: ff26h after reset: ffh r/w symbol 76543210 pm6 pm67 pm66 pm65 pm64 1111 address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 address: ff28h after reset: ffh r/w symbol 76543210 pm8 1111111 pm80 pmmn pmn pin i/o mode selection (m = 0, 2 to 8: n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 120 chapter 6 port functions user s manual u14260ej3v1ud table 6-6. port mode registers and output latch settings when alternate function is used (1/2) pin name p00 to p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 alternate function pm 1 1 1 1 (fix) 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 note 2 p 0 0 0 0 0 0 0 0 note 2 name intp0 to intp2 intp3 adtrg ani0 to ani7 si1 so1 sck1 rxd0 txd0 asck0 sda0 note 1 scl0 note 1 si3 txd2 so3 rxd2 sck3 asck2 ad0 to ad7 a8 to a15 rd wr wait astb i/o input input input input input output input output input output input i/o i/o input output output input input output input i/o output output output input output note 2 note 2 note 2 note 2 note 2 notes 1. pd780078y subseries only 2. when using the p40 to p47, p50 to p57, and p64 to p67 pins as alternate-function pins, set the function using the memory expansion mode register (mem). remark : don t care pm : port mode register p : port register (port output latch) 121 chapter 6 port functions user s manual u14260ej3v1ud table 6-6. port mode registers and output latch settings when alternate function is used (2/2) pin name p70 p71 p72 p73 p74 p75 p80 alternate function pm 1 0 1 1 0 1 0 1 0 1 0 0 1 p 0 0 0 0 0 0 name ti000 to00 ti010 ti50 to50 ti51 to51 ti011 pcl ti001 to01 buz ss1 i/o input output input input output input output input output input output output input remark : don t care pm : port mode register p : port register (port output latch) 122 chapter 6 port functions user s manual u14260ej3v1ud (2) port registers (p0 to p8) these registers write the data that is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. p0 to p8 are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears p0 to p8 to 00h (but p1 is undefined). figure 6-23. format of port register pmn m = 0 to 8; n = 0 to 7 output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level 7 0 symbol p0 6 0 5 0 4 0 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w 7 p17 p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 ff01h 00h (output latch) r/w r 7 0 p2 6 0 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 ff02h undefined 7 0 p3 6 p36 5 p35 4 p34 3 p33 2 p32 1 p31 0 p30 ff03h 00h (output latch) r/w 7 p47 p4 6 p46 5 p45 4 p44 3 p43 2 p42 1 p41 0 p40 ff04h 00h (output latch) r/w 7 p57 p5 6 p56 5 p55 4 p54 3 p53 2 p52 1 p51 0 p50 ff05h 00h (output latch) r/w 7 p67 p6 6 p66 5 p65 4 p64 3 0 2 0 1 0 0 0 ff06h 00h (output latch) r/w 7 0 p7 6 0 5 p75 4 p74 3 p73 2 p72 1 p71 0 p70 ff07h 00h (output latch) r/w 7 0 p8 6 0 5 0 4 0 3 0 2 0 1 0 0 p80 ff08h 00h (output latch) r/w 123 chapter 6 port functions user s manual u14260ej3v1ud (3) pull-up resistor option registers (pu0, pu2 to pu8) these registers are used to set whether to connect an on-chip pull-up resistor at each port or not. by setting pu0 and pu2 to pu8, the on-chip pull-up resistors of the port pins corresponding to the bits in pu0 and pu2 to pu8 can be connected. pu0 and pu2 to pu8 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pu0 and pu2 to pu8 to 00h. cautions 1. the p10 and p17 pins do not incorporate a pull-up resistor. 2. pins p30 to p33 (in the pd780078y subseries, p30 and p31 pins) can be connected to a pull-up resistor via a mask option only for mask rom versions. 3. when pum is set to 1, the on-chip pull-up resistor is connected irrespective of the input/ output mode. when using in output mode, set the bit of pum to 0 (m = 0, 2 to 8). 124 chapter 6 port functions user s manual u14260ej3v1ud figure 6-24. format of pull-up resistor option register (pu0, pu2 to pu8) address: ff30h after reset: 00h r/w symbol 76543210 pu0 0000 pu03 pu02 pu01 pu00 address: ff32h after reset: 00h r/w symbol 76543210 pu2 0 0 pu25 pu24 pu23 pu22 pu21 pu20 address: ff33h after reset: 00h r/w symbol 76543210 pu3 0 pu36 pu35 pu34 0000 address: ff34h after reset: 00h r/w symbol 76543210 pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 address: ff35h after reset: 00h r/w symbol 76543210 pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 address: ff36h after reset: 00h r/w symbol 76543210 pu6 pu67 pu66 pu65 pu64 0000 address: ff37h after reset: 00h r/w symbol 76543210 pu7 0 0 pu75 pu74 pu73 pu72 pu71 pu70 address: ff38h after reset: 00h r/w symbol 76543210 pu8 0000000 pu80 pumn pmn pin on-chip pull-up resistor selection (m = 0, 2 to 8: n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected 125 chapter 6 port functions user s manual u14260ej3v1ud 6.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed in 8-bit units. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 6.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. when a reset is input, the data in the output latch is cleared. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. 6.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 6.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. when a reset is input, the data in the output latch is cleared. (2) input mode the pin level is read and an operation is performed on its contents. the result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. 126 chapter 6 port functions user s manual u14260ej3v1ud 6.5 selection of mask option the following mask option is provided in the mask rom versions. the flash memory versions have no mask options. table 6-7. comparison between mask rom version and flash memory version pin name mask rom version flash memory version mask option for pins p30 to p33 note on-chip pull-up resistors specifiable in 1-bit cannot specify an on-chip pull-up units resistor note for pd780078y subseries products, only the p30 and p31 pins can incorporate a pull-up resistor. 127 user? manual u14260ej3v1ud chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two system clock oscillators are available. (1) main system clock oscillator this circuit oscillates a clock with the following frequencies. ?1 to 8.38 mhz: conventional product of pd780078 subseries and pd780078y subseries ?1 to 12 mhz: expanded-specification product of pd780078 subseries oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). (2) subsystem clock oscillator the circuit oscillates a clock with a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register (pcc). this enables a reduction of power consumption in the stop mode. 7.2 clock generator configuration the clock generator consists of the following hardware. table 7-1. clock generator configuration item configuration control registers processor clock control register (pcc) oscillation stabilization time select register (osts) oscillators main system clock oscillator subsystem clock oscillator controllers prescaler standby controller wait controller 128 chapter 7 clock generator user? manual u14260ej3v1ud figure 7-1. block diagram of clock generator xt1 xt2 frc subsystem clock oscillator f xt main system clock oscillator f x prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 f xt 2 1/2 prescaler standby controller halt wait controller 3 3 stop mcc frc cls osts2 osts1 osts0 css pcc2 pcc1 pcc0 oscillation stabilization time select register (osts) x1 x2 watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) processor clock control register (pcc) internal bus internal bus selector 129 chapter 7 clock generator user s manual u14260ej3v1ud 7.3 clock generator control registers the clock generator is controlled by the following two registers. processor clock control register (pcc) oscillation stabilization time select register (osts) (1) processor clock control register (pcc) pcc selects the cpu clock and the division ratio, sets main system clock oscillator operation/stop and sets whether to use the subsystem clock oscillator internal feedback resistor note . pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 04h. note the feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage. when the subsystem clock is not used, the power consumption in the stop mode can be reduced by setting bit 6 (frc) of pcc to 1 (refer to figure 7-7 subsystem clock feedback resistor ). 130 chapter 7 clock generator user s manual u14260ej3v1ud figure 7-2. format of processor clock control register (pcc) address: fffbh after reset: 04h r/w note 1 symbol 76543210 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc main system clock oscillation control note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock feedback resistor selection 0 internal feedback resistor used 1 internal feedback resistor not used note 3 cls cpu clock status 0 main system clock 1 subsystem clock css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 1000f xt /2 001 010 011 100 other than above setting prohibited notes 1. bit 5 is read only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. the stop instruction should not be used. 3. this bit can be set to 1 only when the subsystem clock is not used. cautions 1. be sure to set bit 3 to 0. 2. when the external clock is input, mcc should not be set. this is because the x2 pin is connected to v dd1 via a pull-up resistor. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 131 chapter 7 clock generator user s manual u14260ej3v1ud the fastest instructions of the pd780078 and 780078y subseries are carried out in two cpu clocks. the relationship between the cpu clock (f cpu ) and minimum instruction execution time is shown in table 7-2. table 7-2. relationship between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x = 8.38 mhz f x = 12 mhz note f xt = 32.768 khz f x 0.238 s 0.166 s ? f x /2 0.477 s 0.333 s ? f x /2 2 0.954 s 0.666 s ? f x /2 3 1.90 s 1.33 s ? f x /2 4 3.81 s 2.66 s ? f xt /2 ?? 122 s note expanded-specification products of pd780078 subseries only remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 132 chapter 7 clock generator user s manual u14260ej3v1ud (2) oscillation stabilization time select register (osts) this register is used to select the oscillation stabilization time from when reset is effected or stop mode is released to when oscillation is stabilized. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. thus, when releasing the stop mode by reset input, the time required to release is 2 17 /fx. figure 7-3. format of oscillation stabilization time select register (osts) address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time f x = 8.38 mhz f x = 12 mhz note 0002 12 /f x 488 s 341 s 0012 14 /f x 1.95 ms 1.36 ms 0102 15 /f x 3.91 ms 2.73 ms 0112 16 /f x 7.82 ms 5.46 ms 1002 17 /f x 15.6 ms 10.9 ms other than above setting prohibited note expanded-specification products of pd780078 subseries only. caution the wait time when stop mode is released does not include the time (??in the figure below) from when stop mode is released until the clock starts oscillation. this also applies when reset is input and an interrupt request is generated. remark f x : main system clock oscillation frequency a stop mode is released voltage waveform of x1 pin 133 chapter 7 clock generator user s manual u14260ej3v1ud 7.4 system clock oscillator 7.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (8.38 mhz typ.) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an inverted-phase clock signal to the x2 pin. figure 7-4 shows an external circuit of the main system clock oscillator. figure 7-4. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock crystal resonator or ceramic resonator x2 v ss1 x1 x2 x1 external clock caution do not execute the stop instruction and do not set mcc (bit 7 of processor clock control register (pcc)) to 1 if an external clock is input. this is because when the stop instruction is executed or mcc is set to 1, the main system clock operation stops and the x2 pin is connected to v dd1 via a pull-up resistor. 134 chapter 7 clock generator user s manual u14260ej3v1ud 7.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (32.768 khz typ.) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator. in this case, input a clock signal to the xt1 pin and an inverted-phase clock signal to the xt2 pin. figure 7-5 shows an external circuit of the subsystem clock oscillator. figure 7-5. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock 32.768 khz xt2 xt1 external clock xt2 v ss1 xt1 cautions are listed on the next page. 135 chapter 7 clock generator user s manual u14260ej3v1ud caution 1. when using the main system clock oscillator and subsystem clock oscillator, wire as follows in the area enclosed by broken lines in figures 7-4 and 7-5 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. figure 7-6 shows examples of incorrect resonator connection. figure 7-6. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. v ss1 v ss1 x2 x1 x2 x1 portn (n = 0 to 8) 136 chapter 7 clock generator user s manual u14260ej3v1ud figure 7-6. examples of incorrect resonator connection (2/2) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) (e) signals are fetched remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunction. to prevent that from occurring, it is recommended to wire x2 and xt1 so that they are not in parallel, and to connect the ic pin between x2 and xt1 directly to v ss1 . x2 v ss1 x1 high current x2 x1 v ss1 abc pnm v dd0 high current v ss1 x2 x1 137 chapter 7 clock generator user s manual u14260ej3v1ud 7.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect directly to v dd0 or v dd1 xt2: leave open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, the above internal feedback resistor can be removed by setting bit 6 (frc) of the processor clock control register (pcc). in this case also, connect the xt1 and xt2 pins as described above. figure 7-7. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2 remark the feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage. 138 chapter 7 clock generator user s manual u14260ej3v1ud 7.5 clock generator operations the clock generator generates the following types of clocks and controls the cpu operating mode including the standby mode. main system clock f x subsystem clock f xt cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined by the processor clock control register (pcc). (a) upon generation of the reset signal, the lowest speed mode of the main system clock (3.81 s @ 8.38 mhz operation) is selected (pcc = 04h). main system clock oscillation stops while a low level is applied to the reset pin. (b) with the main system clock selected, one of the five levels of minimum instruction execution time (0.166 s, 0.333 s, 0.666 s, 1.33 s, 2.66 s: @ 12 mhz operation note , 0.238 s, 0.476 s, 0.954 s, 1.90 s, 3.81 s: @ 8.38 mhz operation) can be selected by setting pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. to reduce power consumption in the stop mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) pcc can be used to select the subsystem clock and to operate the system with low power consumption (122 s @ 32.768 khz operation). (e) with the subsystem clock selected, main system clock oscillation can be stopped via pcc. the halt mode can be used. however, the stop mode cannot be used (subsystem clock oscillation cannot be stopped). (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to the watch timer and clock output functions only. thus the watch function and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation). note expanded-specification products of pd780078 subseries only 139 chapter 7 clock generator user s manual u14260ej3v1ud 7.5.1 main system clock operations when operating with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation-guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of pcc. (b) when bit 4 (css) of pcc is set to 1 when operating with the main system clock, if bit 7 (mcc) of pcc is set to 1 after the operation has been switched to the subsystem clock (cls = 1), the main system clock oscillation stops (see figure 7-8 (1) ). (c) if bit 7 (mcc) of pcc is set to 1 when operating with the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of pcc is set to 1 and the operation is switched to the subsystem clock (cls = 1) after that, the main system clock oscillation stops (see figure 7-8 (2) ). figure 7-8. main system clock stop function (1) operation when mcc is set after setting css with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock (2) operation when css is set after setting mcc with main system clock operation main system clock oscillation subsystem clock oscillation cpu clock mcc css cls oscillation does not stop 140 chapter 7 clock generator user s manual u14260ej3v1ud 7.5.2 subsystem clock operations when operating with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the minimum instruction execution time remains constant (122 s @ 32.768 khz operation) irrespective of bits 0 to 2 (pcc0 to pcc2) of pcc. (b) watchdog timer counting stops. caution do not execute the stop instruction while the subsystem clock is in operation. 7.6 changing system clock and cpu clock settings 7.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc; operation continues on the pre- switchover clock for several instructions (see table 7-3 ). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register. table 7-3. maximum time required for cpu clock switchover remark one instruction is the minimum instruction execution time with the pre-switchover cpu clock. caution selection of the cpu clock cycle division ratio (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle division ratio (pcc0 to pcc2) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). set value before set value after switchover switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0000 00 01001000 1101001 0000 16 instructions 16 instructions 16 instructions 16 instructions f x /2f xt instruction 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions f x /4f xt instruction 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions f x /8f xt instruction 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions f x /16f xt instruction 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction f x /32f xt instruction 1 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 141 chapter 7 clock generator user s manual u14260ej3v1ud 7.6.2 system clock and cpu clock switching procedure this section describes procedure for switching between the system clock and cpu clock. figure 7-9. system clock and cpu clock switching <1> the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, the main system clock starts oscillation. at this time, the oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing instructions at the minimum speed of the main system clock (3.81 s @ 8.38 mhz operation). <2> after the lapse of sufficient time for the v dd voltage to increase to enable operation at maximum speeds, pcc is rewritten and maximum-speed operation is carried out. <3> upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). <4> upon detection of v dd voltage reset due to an interrupt, 0 is set to the mcc and oscillation of the main system clock is started. after the lapse of the time required for stabilization of oscillation, pcc is rewritten and the maximum-speed operation is resumed. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. system clock cpu clock interrupt request signal reset v dd f x f x f xt f x lowest- speed operation highest- speed operation subsystem clock operation high-speed operation wait (15.6 ms: @8.38 mhz operation) internal reset operation 142 user? manual u14260ej3v1ud chapter 8 16-bit timer/event counters 00, 01 8.1 functions of 16-bit timer/event counters 00, 01 16-bit timer/event counters 00, 01 have the following functions. (1) interval timer 16-bit timer/event counters 00, 01 generate interrupt requests at the preset time interval. number of counts: 2 to 65536 (2) external event counter 16-bit timer/event counters 00, 01 can measure the number of pulses with a high-/low-level width of a signal input externally. valid level pulse width: 16/f x or more (3) pulse width measurement 16-bit timer/event counters 00, 01 can measure the pulse width of an externally input signal. valid level pulse width: 2/f x or more (4) square-wave output 16-bit timer/event counters 00, 01 can output a square wave with any selected frequency. cycle: (2 2 to 65536 2) count clock cycle (5) ppg output 16-bit timer/event counters 00, 01 can output a square wave that have arbitrary cycle and pulse width. 2 < pulse width < cycle (ffff + 1) h 143 chapter 8 16-bit timer/event counters 00, 01 user? manual u14260ej3v1ud 8.2 configuration of 16-bit timer/event counters 00, 01 16-bit timer/event counters 00, 01 consist of the following hardware. table 8-1. configuration of 16-bit timer/event counters 00, 01 item configuration timer counter 16-bit timer counter 0n (tm0n) register 16-bit timer capture/compare registers 00n, 01n (cr00n, cr01n) timer input ti00n, ti01n timer output to0n, output controller control registers 16-bit timer mode control register 0n (tmc0n) capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 7 (pm7) port register 7 (p7) remark n = 0, 1 figures 8-1 and 8-2 show the block diagrams. figure 8-1. block diagram of 16-bit timer/event counter 00 note ti000 input and to00 output cannot be used at the same time. capture/compare control register 00 (crc00) prescaler mode register 00 (prm00) 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus ti010/p71 f x f x /2 2 f x /2 6 f x /2 3 ti000/to00/p70 note 2 noise elimi- nator prm010 prm000 crc020 match match clear noise elimi- nator noise elimi- nator crc020 crc010 crc000 inttm000 to00/ti000/ p70 note inttm010 internal bus tmc003 tmc002 ovf00 toc040 lvs00 lvr00 toc010 toe00 output latch (p70) pm70 selector selector selector selector 16-bit timer capture/compare register 010 (cr010) 16-bit timer counter 00 (tm00) 16-bit timer capture/compare register 000 (cr000) output controller 144 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-2. block diagram of 16-bit timer/event counter 01 note ti001 input and to01 output cannot be used at the same time. ti011/pcl/p74 f x /2 f x /2 3 f x /2 9 f x /2 3 ti001/to01/ buz/p75 note 2 prm011 prm001 crc021 crc021 crc011 crc001 inttm001 inttm011 tmc013 tmc012 ovf01 toc041 lvs01 lvr01 toc011 toe01 to01/ti001/ buz/p75 note pm75 capture/compare control register 01 (crc01) prescaler mode register 01 (prm01) 16-bit timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus noise elimi- nator match match clear noise elimi- nator noise elimi- nator internal bus output latch (p75) selector selector selector selector 16-bit timer capture/compare register 011 (cr011) 16-bit timer counter 01 (tm01) 16-bit timer capture/compare register 001 (cr001) output controller 145 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. figure 8-3. format of 16-bit timer counter 0n (tm0n) the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc0n3 and tmc0n2 are cleared <3> if the valid edge of ti00n is input in the clear & start mode entered by inputting the valid edge of ti00n <4> if tm0n and cr00n match in the clear & start mode entered on a match between tm0n and cr00n (2) 16-bit timer capture/compare register 00n (cr00n) cr00n is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00n) of capture/compare control register 0n (crc0n). cr00n is set by a 16-bit memory manipulation instruction. reset input clears cr00n to 0000h. figure 8-4. format of 16-bit timer capture/compare register 00n (cr00n) when cr00n is used as a compare register the value set in cr00n is constantly compared with the 16-bit timer/counter 0n (tm0n) count value, and an interrupt request (inttm00n) is generated if they match. it can also be used as the register that holds the interval time when tm0n is set to interval timer operation. when cr00n is used as a capture register it is possible to select the valid edge of the ti00n pin or the ti01n pin as the capture trigger. setting of the ti00n or ti01n valid edge is performed by means of prescaler mode register 0n (prm0n) (refer to table 8-2 ). tm0n (n = 0, 1) symbol ff0fh (tm00) ff6dh (tm01) ff0eh (tm00) ff6ch (tm01) address: ff0eh, ff0fh (tm00), ff6ch, ff6dh (tm01) after reset: 0000h r cr00n (n = 0, 1) symbol ff0bh (cr000) ff69h (cr001) ff0ah (cr000) ff68h (cr001) address: ff0ah, ff0bh (cr000), ff68h, ff69h (cr001) after reset: 0000h r/w 146 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud table 8-2. cr00n capture trigger and valid edges of ti00n and ti01n pins (1) ti00n pin valid edge selected as capture trigger (crc01n = 1, crc00n = 1) cr00n capture trigger ti00n pin valid edge es01n es00n falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti01n pin valid edge selected as capture trigger (crc01n = 0, crc00n = 1) cr00n capture trigger ti01n pin valid edge es11n es10n falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es01n, es00n = 1, 0 and es11n, es10n = 1, 0 is prohibited. 2. es01n, es00n: bits 5 and 4 of prescaler mode register 0n (prm0n) es11n, es10n: bits 7 and 6 of prescaler mode register 0n (prm0n) crc01n, crc00n: bits 1 and 0 of capture/compare control register 0n (crc0n) 3. n = 0, 1 cautions 1. set cr00n to a value other than 0000h in the clear & start mode entered on a match between tm0n and cr00n. however, in the free-running mode and in the clear & start mode using the valid edge of the ti00n pin, if cr00n is set to 0000h, an interrupt request (inttm00n) is generated when cr00n changes from 0000h to 0001h following overflow (ffffh). 2. if the new value of cr00n is less than the value of 16-bit timer counter 0n (tm0n), tm0n continues counting, overflows, and then starts counting from 0 again. if the new value of cr00n is less than the old value, therefore, the timer must be reset to be restarted after the value of cr00n is changed. 3. when p70 is used as the input pin for the valid edge of ti000, it cannot be used as a timer output (to00). moreover, when p70 is used as to00, it cannot be used as the input pin for the valid edge of ti000. 4. when p75 is used as the input pin for the valid edge of ti001, it cannot be used as a timer output (to01). moreover, when p75 is used as to01, it cannot be used as the input pin for the valid edge of ti001. 5. when cr00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. 147 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (3) 16-bit timer capture/compare register 01n (cr01n) cr01n is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02n) of capture/compare control register 0n (crc0n). cr01n is set by a 16-bit memory manipulation instruction. reset input clears cr01n to 0000h. figure 8-5. format of 16-bit timer capture/compare register 01n (cr01n) when cr01n is used as a compare register the value set in cr01n is constantly compared with the 16-bit timer counter 0n (tm0n) count value, and an interrupt request (inttm01n) is generated if they match. when cr01n is used as a capture register it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti00n valid edge is set by means of prescaler mode register 0n (prm0n) (refer to table 8-3 ). table 8-3. cr01n capture trigger and valid edge of ti00n pin (crc02n = 1) cr01n capture trigger ti00n pin valid edge es01n es00n falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es01n, es00n = 1, 0 is prohibited. 2. es01n, es00n: bits 5 and 4 of prescaler mode register 0n (prm0n) crc02n: bit 2 of capture/compare control register 0n (crc0n) 3. n = 0, 1 cautions 1. if cr01n is set to 0000h, an interrupt request (inttm01n) is generated when cr01n changes from 0000h to 0001h following overflow (ffffh). inttm01n is generated after the match between tm0n and cr01n or after the valid edge of the ti00n pin is detected. 2. when cr01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). if count stop input and capture trigger input conflict, the captured data is undefined. remark n = 0, 1 cr01n (n = 0, 1) symbol ff0dh (cr010) ff6bh (cr011) ff0ch (cr010) ff6ah (cr011) address: ff0ch, ff0dh (cr010), ff6ah, ff6bh (cr011) after reset: 0000h r/w 148 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.3 registers to control 16-bit timer/event counters 00, 01 the following six types of registers are used to control 16-bit timer/event counters 00, 01. 16-bit timer mode control register 0n (tmc0n) capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 7 (pm7) port register 7 (p7) remark n = 0, 1 (1) 16-bit timer mode control register 0n (tmc0n: n = 0, 1) this register sets the 16-bit timer operating mode, the 16-bit timer counter 0n (tm0n) clear mode, and output timing, and detects an overflow. tmc0n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0n to 00h. caution 16-bit timer counter 0n (tm0n) starts operation at the moment tmc0n2 and tmc0n3 (operation stop mode) are set to a value other than 0, 0, respectively. set tmc0n2 and tmc0n3 to 0, 0 to stop the operation. 149 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-6. format of 16-bit timer mode control register 00 (tmc00) tmc003 tmc002 operating mode to00 inversion timing selection interrupt request generation and clear mode selection 0 0 operation stop no change not generated (tm00 cleared to 0) 0 1 free-running mode match between tm00 and cr000 or match between tm00 and cr010 1 0 clear & start on ti000 pin valid edge 11 clear & start on match between match between tm00 and tm00 and cr000 cr000 or match between tm00 and cr010 ovf00 overflow detection of 16-bit timer counter 00 (tm00) 0 overflow not detected 1 overflow detected cautions 1. to write different data to tmc00, stop the timer operation before writing. 2. the timer operation must be stopped before writing to bits other than the ovf00 flag. 3. set the valid edge of the ti000/to00/p70 pin with prescaler mode register 00 (prm00). 4. if any of the following modes is selected: the mode in which clear & start occurs on match between tm00 and cr000, the mode in which clear & start occurs at the ti000 pin valid edge, or free-running mode, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. remarks 1. to00: 16-bit timer/event counter 00 output pin 2. ti000: 16-bit timer/event counter 00 input pin 3. tm00: 16-bit timer counter 00 4. cr000: 16-bit timer capture/compare register 000 5. cr010: 16-bit timer capture/compare register 010 generated on match between tm00 and cr000, or match between tm00 and cr010 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 0 0 ovf00 symbol tmc00 address: ff60h after reset: 00h r/w 150 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-7. format of 16-bit timer mode control register 01 (tmc01) tmc013 tmc012 operating mode to01 output timing selection interrupt request generation and clear mode selection 0 0 operation stop no change not generated (tm01 cleared to 0) 0 1 free-running mode match between tm01 and cr001 or match between tm01 and cr011 1 0 clear & start on ti001 pin valid edge 11 clear & start on match between match between tm01 and tm01 and cr001 cr001 or match between tm01 and cr011 ovf01 overflow detection of 16-bit timer counter 01 (tm01) 0 overflow not detected 1 overflow detected cautions 1. to write different data to tmc01, stop the timer operation before writing. 2. the timer operation must be stopped before writing to bits other than the ovf01 flag. 3. set the valid edge of the ti001/to01/buz/p75 pin with prescaler mode register 01 (prm01). 4. if any of the following modes is selected: the mode in which clear & start occurs on match between tm01 and cr001, the mode in which clear & start occurs at the ti001 pin valid edge, or free-running mode, when the set value of cr001 is ffffh and the tm01 value changes from ffffh to 0000h, the ovf01 flag is set to 1. remarks 1. to01: 16-bit timer/event counter 01 output pin 2. ti001: 16-bit timer/event counter 01 input pin 3. tm01: 16-bit timer counter 01 4. cr001: 16-bit timer capture/compare register 001 5. cr011: 16-bit timer capture/compare register 011 generated on match between tm01 and cr001, or match between tm01 and cr011 7 0 6 0 5 0 4 0 3 tmc013 2 tmc012 1 0 0 ovf01 symbol tmc01 address: ff64h after reset: 00h r/w 151 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (2) capture/compare control register 0n (crc0n: n = 0, 1) this register controls the operation of the 16-bit timer capture/compare registers (cr00n, cr01n). crc0n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0n to 00h. figure 8-8. format of capture/compare control register 00 (crc00) address: ff62h after reset: 00h r/w symbol 76543210 crc00 00000 crc020 crc010 crc000 crc020 cr010 operating mode selection 0 operate as compare register 1 operate as capture register crc010 cr000 capture trigger selection 0 capture on valid edge of ti010 pin 1 capture on valid edge of ti000 pin by reverse phase crc000 cr000 operating mode selection 0 operate as compare register 1 operate as capture register cautions 1. the timer operation must be stopped before setting crc00. 2. when the clear & start mode entered on a match between tm00 and cr000 is selected by 16-bit timer mode control register 00 (tmc00), cr000 should not be specified as a capture register. 3. if both the rising and falling edges have been selected as the valid edges of the ti000 pin, capture is not performed. 4. to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (prm00) (refer to figure 8-22). 152 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-9. format of capture/compare control register 01 (crc01) address: ff66h after reset: 00h r/w symbol 76543210 crc01 00000 crc021 crc011 crc001 crc021 cr011 operating mode selection 0 operate as compare register 1 operate as capture register crc011 cr001 capture trigger selection 0 capture on valid edge of ti011 pin 1 capture on valid edge of ti001 pin by reverse phase crc001 cr001 operating mode selection 0 operate as compare register 1 operate as capture register cautions 1. the timer operation must be stopped before setting crc01. 2. when the clear & start mode entered on a match between tm01 and cr001 is selected by 16-bit timer mode control register 01 (tmc01), cr001 should not be specified as a capture register. 3. if both the rising and falling edges have been selected as the valid edges of the ti001 pin, capture is not performed. 4. to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 01 (prm01) (refer to figure 8-22). 153 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (3) 16-bit timer output control register 0n (toc0n: n = 0, 1) this register controls the operation of the 16-bit timer/event counter output controller. it sets timer output f/f set/ reset, output inversion enable/disable, and 16-bit timer/event counter 0n timer output enable/disable. toc0n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0n to 00h. figure 8-10. format of 16-bit timer output control register 00 (toc00) address: ff63h after reset: 00h r/w symbol 76543210 toc00 0 0 0 toc040 lvs00 lvr00 toc010 toe00 toc040 timer output f/f control by match of cr010 and tm00 0 inversion operation disabled 1 inversion operation enabled lvs00 lvr00 16-bit timer/event counter 00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc010 timer output f/f control by match of cr000 and tm00 0 inversion operation disabled 1 inversion operation enabled toe00 16-bit timer/event counter 00 output control 0 output disabled (output set to level 0) 1 output enabled cautions 1. the timer operation must be stopped before setting other than toc040. 2. if lvs00 and lvr00 are read after data is set, they will be 0. 3. bits 5 to 7 of toc00 must be set to 0. 154 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-11. format of 16-bit timer output control register 01 (toc01) address: ff67h after reset: 00h r/w symbol 76543210 toc01 0 0 0 toc041 lvs01 lvr01 toc011 toe01 toc041 timer output f/f control by match of cr011 and tm01 0 inversion operation disabled 1 inversion operation enabled lvs01 lvr01 16-bit timer/event counter 01 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc011 timer output f/f control by match of cr001 and tm01 0 inversion operation disabled 1 inversion operation enabled toe01 16-bit timer/event counter 01 output control 0 output disabled (output set to level 0) 1 output enabled cautions 1. the timer operation must be stopped before setting toc041. 2. if lvs01 and lvr01 are read after data is set, they will be 0. 3. bits 5 to 7 of toc01 must be set to 0. 155 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (4) prescaler mode register 0n (prm0n: n = 0, 1) this register is used to set the 16-bit timer counter 0n (tm0n) count clock and ti00n, ti01n pin input valid edges. prm0n is set by an 8-bit memory manipulation instruction. reset input clears prm0n to 00h. figure 8-12. format of prescaler mode register 00 (prm00) address: ff61h after reset: 00h r/w symbol 76543210 prm00 es110 es100 es010 es000 0 0 prm010 prm000 es110 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es010 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm010 prm000 count clock selection f x = 8.38 mhz f x = 12 mhz note 1 00f x 8.38 mhz 12 mhz 01f x /2 2 2.09 mhz 3 mhz 10f x /2 6 130 khz 187 khz 1 1 ti000 pin valid edge notes 2, 3 notes 1. expanded-specification products of pd780078 subseries only. 2. the external clock requires a pulse two cycles longer than internal clock (f x /2 3 ). 3. when the valid edge of the ti000 pin is selected, the main system clock is used as the sampling clock for noise elimination. the valid edge of the ti000 pin can be used only when the main system clock is operating. cautions 1. always set data to prm00 after stopping the timer operation. 2. if the valid edge of the ti000 pin is to be set as the count clock, do not set the clear & start mode and the capture trigger at the valid edge of the ti000 pin. 3. when p70 is used as the valid edge of the ti000 pin, it cannot be used as the timer output (to00 pin), and when used as the to00 pin, it cannot be used as the valid edge of the ti000 pin. 4. if the ti000 or ti010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to enable the operation of 16-bit timer counter 00 (tm00). be careful when pulling up the ti000 pin or the ti010 pin. however, when re- enabling operation after the operation has been stopped once, the rising edge is not detected. remarks 1. f x : main system clock oscillation frequency 2. ti000 or ti010 pin: 16-bit timer/event counter 00 input pin 156 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-13. format of prescaler mode register 01 (prm01) address: ff65h after reset: 00h r/w symbol 76543210 prm01 es111 es101 es011 es001 0 0 prm011 prm001 es111 es101 ti011 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es001 ti001 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm011 prm001 count clock selection f x = 8.38 mhz f x = 12 mhz note 1 00f x /2 4.19 mhz 6 mhz 01f x /2 3 1.04 mhz 1.5 mhz 10f x /2 9 16.36 khz 23.43 khz 1 1 ti001 pin valid edge notes 2, 3 notes 1. expanded-specification products of pd780078 subseries only. 2. the external clock requires a pulse two cycles longer than internal clock (f x /2 3 ). 3. when the valid edge of the ti001 pin is selected, the main system clock is used as the sampling clock for noise elimination. the valid edge of the ti001 pin can be used only when the main system clock is operating. cautions 1. always set data to prm01 after stopping the timer operation. 2. if the valid edge of the ti001 pin is to be set as the count clock, do not set the clear & start mode and the capture trigger at the valid edge of the ti001 pin. 3. when p75 is used as the valid edge of the ti001 pin, it cannot be used as the timer output (to01 pin), and when used as the to01 pin, it cannot be used as the valid edge of the ti001 pin. 4. if the ti001 or ti011 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edge are set as the valid edge(s) of the ti001 pin or ti011 pin to enable the operation of 16-bit timer counter 01 (tm01). be careful when pulling up the ti001 pin or the ti011 pin. however, when re- enabling operation after the operation has been stopped once, the rising edge is not detected. remarks 1. f x : main system clock oscillation frequency 2. ti001 or ti011 pin: 16-bit timer/event counter 01 input pin 157 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (5) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p70/to00/ti000 and p75/to01/ti001/buz pins for timer output, set pm70 and pm75, and the output latches of p70 and p75 to 0. when using the p70/to00/ti000 and p75/to01/ti001/buz pins for timer input, set pm70 and pm75 to 1. at this time, the output latches of p70 and p75 can be either 0 or 1. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 8-14. format of port mode register 7 (pm7) 7 1 6 1 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 symbol pm7 address: ff27h after reset: ffh r/w pm7n 0 1 p7n pin i/o mode selection (n = 0 to 5) output mode (output buffer on) input mode (output buffer off) 158 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.4 operation of 16-bit timer/event counters 00, 01 8.4.1 interval timer operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 8-15 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 8-15 for the set value). <2> set any value to the cr00n register. <3> set the count clock by using the prm0n register. <4> set the tmc0n register to start the operation (see figure 8-15 for the set value). remark for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 00n (cr00n) beforehand as the interval. when the count value of 16-bit timer counter 0n (tm0n) matches the value set to cr00n, counting continues with the tm0n value cleared to 0 and the interrupt request signal (inttm00n) is generated. the count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (prm00n, prm01n) of prescaler mode register 0n (prm0n). figure 8-15. control register settings for interval timer operation (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) prescaler mode register 0n (prm0n) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 1 0 ovfn0 0 tmc0n clears and starts on match between tm0n and cr00n. 7 0 6 0 5 0 4 0 3 0 crc02n 0/1 crc01n 0/1 crc00n 0 crc0n cr00n used as compare register es11n 0/1 es10n 0/1 es01n 0/1 es00n 0/1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock. setting invalid (setting 10 is prohibited.) setting invalid (setting 10 is prohibited.) 159 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-16. interval timer configuration diagram notes 1. the values outside parentheses apply to 16-bit timer/event counter 00, and the values in parentheses apply to 16-bit timer/event counter 01. 2. ovf0n is 1 only when 16-bit timer capture/compare register 00n is set to ffffh. figure 8-17. timing of interval timer operation remarks 1. interval time = (n + 1) t n = 0001h to ffffh 2. n = 0, 1 16-bit timer capture/compare register 00n 16-bit timer counter 0n ovf0n note 2 clear circuit inttm00n f x (f x /2) note 1 f x /2 2 (f x /2 3 ) note 1 f x /2 6 (f x /2 9 ) note 1 ti000/to00/p70 (ti001/to01/buz/p75) note 1 selector noise eliminator f x /2 3 count clock t tm0n count value cr00n inttm00n 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt acknowledged interrupt acknowledged 160 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud when the compare register is changed during timer count operation, if the value after 16-bit timer capture/ compare register 00n (cr00n) is changed is smaller than that of 16-bit timer counter 0n (tm0n), tm0n continues counting, overflows and then restarts counting from 0. thus, if the value (m) after the cr00n change is smaller than that (n) before the change, it is necessary to restart the timer after changing cr00n. figure 8-18. timing after change of compare register during timer count operation cr00n nm count clock tm0n count value x 1 x ffffh 0000h 0001h 0002h remark n > x > m n = 0, 1 161 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.4.2 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 8-19 for the set value). <2> set the count clock by using the prm0n register. <3> set any value to the cr00n register (0000h cannot be set). <4> set the tmc0n register to start the operation (see figure 8-19 for the set value). remarks 1. for the setting of the ti00n pin, see 8.3 (5) port mode register 7 (pm7) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . the external event counter counts the number of external clock pulses to be input to the ti00n pin with using 16- bit timer counter 0n (tm0n). tm0n is incremented each time the valid edge specified by prescaler mode register 0n (prm0n) is input. when the tm0n count value matches the 16-bit timer capture/compare register 00n (cr00n) value, tm0n is cleared to 0 and the interrupt request signal (inttm00n) is generated. input a value other than 0000h to cr00n (a count operation with a pulse cannot be carried out). the rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (es00n and es01n) of prescaler mode register 0n (prm0n). because an operation is carried out only when the valid level of the ti00n pin is detected twice after sampling with the internal clock (f x /2 3 ), noise with a short pulse width can be eliminated. caution when used as an external event counter, the p70/ti000/to00 or p75/ti001/to01/buz pin cannot be used as a timer output (to00, to01). figure 8-19. control register settings in external event counter mode (with rising edge specified) (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) prescaler mode register 0n (prm0n) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respective control registers for details. n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 7 0 6 0 5 0 4 0 3 0 crc02n 0/1 crc01n 0/1 crc00n 0 crc0n cr00n used as compare register es11n 0/1 es10n 0/1 es01n 0 es00n 1 3 0 2 0 prm01n 1 prm00n 1 prm0n selects external clock. specifies rising edge for pulse width detection. setting invalid (setting 10 is prohibited.) 162 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-20. external event counter configuration diagram 16-bit timer capture/compare register 00n 16-bit timer counter 0n (tm0n) internal bus match clear ovf0n note inttm00n noise eliminator f x /2 3 valid edge of ti00n note ovf0n is 1 only when 16-bit timer capture/compare register 00n is set to ffffh. figure 8-21. external event counter operation timing (with rising edge specified) ti00n pin input tm0n count value cr00n inttm00n 0000h 0001h 0002h 0003h 0004h 0005h n 1n 0000h 0001h 0002h 0003h n caution when reading the external event counter count value, tm0n should be read. remark n = 0, 1 163 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00n pin and ti01n pin using 16-bit timer counter 0n (tm0n). there are two measurement methods: measuring with tm0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00n pin. when an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 0n (prm0n) and the valid level of the ti00n or ti01n pin is detected twice, thus eliminating noise with a short pulse width. figure 8-22. cr01n capture operation with rising edge specified setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figures 8-23 , 8-26 , 8-28 , and 8-30 for the set value). <2> set the count clock by using the prm0n register. <3> set the tmc0n register to start the operation (see figures 8-23 , 8-26 , 8-28 , and 8-30 for the set value). caution to use two capture registers, set the ti00n and ti01n pins. remarks 1. for the setting of the ti00n (or ti01n) pin, see 8.3 (5) port mode register 7 (pm7) . 2. for how to enable the inttm00n (or inttm01n) interrupt, see chapter 19 interrupt functions . 3. n = 0, 1 count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n + 1 n 164 chapter 8 16-bit timer/event counters 00, 01 user? manual u14260ej3v1ud (1) pulse width measurement with free-running counter and one capture register when 16-bit timer counter 0n (tm0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. the both falling and rising edges can be specified by bits 4 and 5 (es00n and es01n) of prm0n. sampling is performed with the count clock selected by prm0n, and a capture operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. figure 8-23. control register settings for pulse width measurement with free-running counter and one capture register (when ti00n and cr01n are used) (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) prescaler mode register 0n (prm0n) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. n = 0, 1 7 0 6 0 5 0 4 0 3 0 crc02n 1 crc01n 0/1 crc00n 0 crc0n cr00n used as compare register cr01n used as capture register es11n 0/1 es10n 0/1 es01n 1 es00n 1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock (setting 11 is prohibited). specifies both edges for pulse width detection. setting invalid (setting 10 is prohibited.) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 1 0 ovf0n 0 tmc0n free-running mode 165 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-24. configuration diagram for pulse width measurement with free-running counter note values outside parentheses apply to 16-bit timer/event counter 00, and values in parentheses apply to 16- bit timer/event counter 01. figure 8-25. timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) note ovf0n must be cleared by software. remark n = 0, 1 f x (f x /2) note f x /2 2 (f x /2 3 ) note f x /2 6 (f x /2 9 ) note ti000/to00/p70 (ti001/to01/buz/p75) note 16-bit timer/counter 0n ovf0n 16-bit timer capture/compare register 01n internal bus inttm01n selector t 0000h 0000h ffffh 0001h d0 d0 (d1 d0) t (d3 d2) t (10000h d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1 note count clock tm0n count value ti00n pin input cr01n capture value inttm01n ovf0n 166 chapter 8 16-bit timer/event counters 00, 01 user? manual u14260ej3v1ud (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0n (tm0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the ti00n pin and the ti01n pin. when the edge specified by bits 4 and 5 (es00n and es01n) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the edge specified by bits 6 and 7 (es10n and es11n) of prm0n is input to the ti01n pin, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n) and an external interrupt request signal (inttm00n) is set. the both falling and rising edges can be specified as the valid edges for the ti00n pin and the ti01n pin by bits 4 and 5 (es00n and es01n) and bits 6 and 7 (es10n and es11n) of prm0n, respectively. sampling is performed with the count clock cycle selected by prescaler mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n pin or ti01n pin is detected twice, thus eliminating noise with a short pulse width. figure 8-26. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) prescaler mode register 0n (prm0n) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 1 0 ovf0n 0 tmc0n free-running mode 7 0 6 0 5 0 4 0 3 0 crc02n 1 crc01n 0 crc00n 1 crc0n cr00n used as capture register captures valid edge of ti01n pin to cr00n cr01n used as capture register es11n 1 es10n 1 es01n 1 es00n 1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock (setting 11 is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. 167 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-27. timing of pulse width measurement operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 (d1 d0) t (d3 d2) t (10000h d1 + d2) t (10000h d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 note ti01n pin input cr00n capture value inttm01n inttm00n ovf0n count clock tm0n count value ti00n pin input cr01n capture value note ovf0n must be cleared by software. remark n = 0, 1 168 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 0n (tm0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the ti00n pin. when the rising or falling edge specified by bits 4 and 5 (es00n and es01n) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the inverse edge to that of the capture operation to cr01n is input, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n). sampling is performed with the count clock cycle selected by prescaler mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of the ti00n pin is specified to be both the rising and falling edges, 16-bit timer capture/compare register 00n (cr00n) cannot perform the capture operation. figure 8-28. control register settings for pulse width measurement with free-running counter and two capture registers (with rising edge specified) (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) prescaler mode register 0n (prm0n) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 1 0 ovf0n 0 tmc0n free-running mode 7 0 6 0 5 0 4 0 3 0 crc02n 1 crc01n 1 crc00n 1 crc0n cr00n used as capture register captures to cr00n at edge reverse to valid edge of ti00n pin. cr01n used as capture register es11n 0/1 es10n 0/1 es01n 0 es00n 1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock (setting 11 is prohibited). specifies rising edge for pulse width detection. setting invalid (setting 10 is prohibited.) 169 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-29. timing of pulse width measurement operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 d2 d1 d3 d2 d3 d1 d0 + 1 d2 + 1 d1 + 1 inttm01n ovf0n cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value (d1 d0) t (d3 d2) t (10000h d1 + d2) t note note ovf0n must be cleared by software. (4) pulse width measurement by means of restart when input of a valid edge to the ti00n pin is detected, the count value of 16-bit timer/counter 0n (tm0n) is taken into 16-bit timer capture/compare register 01n (cr01n), and then the pulse width of the signal input to the ti00n pin is measured by clearing tm0n and restarting the count. the edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (es00n and es01n) of prescaler mode register 0n (prm0n). sampling is performed with the count clock cycle selected by prescaler mode register 0n (prm0n) and a capture operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of the ti00n pin is specified to be both the rising and falling edges, 16-bit timer capture/compare register 00n (cr00n) cannot perform the capture operation. remark n = 0, 1 170 chapter 8 16-bit timer/event counters 00, 01 user? manual u14260ej3v1ud figure 8-30. control register settings for pulse width measurement by means of restart (with rising edge specified) (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) prescaler mode register 0n (prm0n) figure 8-31. timing of pulse width measurement operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 d2 d1 d2 d1 d1 t d2 t inttm01n cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value remark n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 0 1 0 ovf0n 0 tmc0n clears and starts at valid edge of ti00n pin. 7 0 6 0 5 0 4 0 3 0 crc02n 1 crc01n 1 crc00n 1 crc0n cr00n used as capture register captures to cr00n at edge reverse to valid edge of ti00n pin. cr01n used as capture register es11n 0/1 es10n 0/1 es01n 0 es00n 1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock (setting 11 is prohibited). specifies rising edge for pulse width detection. setting invalid (setting 10 is prohibited.) 171 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.4.4 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figure 8-32 for the set value). <3> set the toc0n register (see figure 8-32 for the set value). <4> set any value to the cr00n register (0000h cannot be set). <5> set the tmc0n register to start the operation (see figure 8-32 for the set value). remarks 1. for the setting of the to0n pin, see 8.3 (5) port mode register 7 (pm7) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16-bit timer capture/compare register 00n (cr00n). the to0n pin output status is reversed at intervals determined by the count value preset to cr00n + 1 by setting bit 0 (toe0n) and bit 1 (toc01n) of 16-bit timer output control register 0n (toc0n) to 1. this enables a square wave with any selected frequency to be output. figure 8-32. control register settings in square-wave output mode (1/2) (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) remark n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 7 0 6 0 5 0 4 0 3 0 crc02n 0/1 crc01n 0/1 crc00n 0 crc0n cr00n used as compare register 172 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 7 0 6 0 5 0 toc04n 0 lvs0n 0/1 lvr0n 0/1 toc01n 1 toe0n 1 toc0n enables to0n output. reverses output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting 11 is prohibited). does not reverse output on match between tm0n and cr01n. es11n 0/1 es10n 0/1 es01n 0/1 es00n 0/1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock. setting invalid (setting 10 is prohibited.) setting invalid (setting 10 is prohibited.) figure 8-32. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 0n (toc0n) (d) prescaler mode register 0n (prm0n) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. n = 0, 1 figure 8-33. square-wave output operation timing count clock tm0n count value cr00n inttm00n to0n pin output 0000h 0001h 0002h n 1n 0000h 0001h 0002h n 1n 0000h n remark n = 0, 1 173 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.4.5 ppg output operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 8-34 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 8-34 for the set value). <2> set any value to the cr00n register as the cycle. <3> set any value to the cr01n register as the duty factor. <4> set the toc0n register (see figure 8-34 for the set value). <5> set the count clock by using the prm0n register. <6> set the tmc0n register to start the operation (see figure 8-34 for the set value). remarks 1. for the setting of the to0n pin, see 8.3 (5) port mode register 7 (pm7) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . in the ppg output operation, square waves are output from the to0n pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit timer capture/compare register 01n (cr01n) and in 16-bit timer capture/compare register 00n (cr00n), respectively. remark n = 0, 1 174 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-34. control register settings for ppg output operation (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) 16-bit timer output control register 0n (toc0n) (d) prescaler mode register 0n (prm0n) cautions 1. cr00n and cr01n values in the following range should be set to: 0000h cr01n < cr00n ffffh 2. the cycle of the pulse generated via ppg output (cr00n setting value + 1) has a duty of (cr01n setting value + 1)/(cr00n setting value + 1). remarks 1. : don t care 2. n = 0, 1 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 7 0 6 0 5 0 4 0 3 0 crc02n 0 crc01n crc00n 0 crc0n cr00n used as compare register cr01n used as compare register es11n 0/1 es10n 0/1 es01n 0/1 es00n 0/1 3 0 2 0 prm01n 0/1 prm00n 0/1 prm0n selects count clock. setting invalid (setting 10 is prohibited.) setting invalid (setting 10 is prohibited.) 7 0 6 0 5 0 toc04n 1 lvs0n 0/1 lvr0n 0/1 toc01n 1 toe0n 1 toc0n enables to0n output. reverses output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting 11 is prohibited). reverses output on match between tm0n and cr01n. 175 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-35. ppg output configuration diagram note values outside parentheses apply to 16-bit timer/event counter 00, and values in the parentheses apply to 16-bit timer/event counter 01. figure 8-36. ppg output operation timing remark 0000h m < n ffffh n = 0, 1 16-bit timer capture/ compare register 00n 16-bit timer counter 0n clear circuit f x (f x /2) note f x /2 2 (f x /2 3 ) note f x /2 6 (f x /2 9 ) note 16-bit timer capture/compare register 01n to00/ti000/p70 (to01/ti001/p75) note selector output controller t 0000h 0000h 0001h 0001h m ? 1 count clock tm0n count value to0n pulse width: (m + 1) t 1 cycle: (n + 1) t n cr00n capture value cr01n capture value m m n ? 1 n n clear clear 176 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.5 program list caution the following sample program is shown as an example to describe the operation of semiconductor products and their applications. therefore, when applying the following information to your devices, design the devices after performing evaluation under your own responsibility. 177 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.5.1 interval timer /*******************************************************************************/ /* */ /* setting example of timer 00 interval timer mode */ /* cycle set to 130 as intervaltm00 (at 8.38 mhz for 1 ms) */ /* variable ppgdata prepared as rewrite data area */ /* : cycle (if 0000, no change) */ /* ppgdata to be checked at every inttm000, and changed if required. */ /* therefore, if change is required, set the change data in ppgdata. */ /* when changed, ppgdata cleared to 0000. */ /* */ /*******************************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm00 130 /* cycle data to be set to cr000 */ #pragma interrupt inttm000 intervalint rb2 unsigned int ppgdata; /* data area to be set to timer 00 */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ ppgdata = 0; /* set port */ /* set the following to output */ p7 = 0b11111110; /* clear p70 */ pm7.0 = 0; /* set p70 as output */ /* set interrupt */ tmmk000 = 0; /* cancel inttm000 interrupt mask */ /* set timer 00 */ prm00 = 0b00000010; /* count clock is fx/2^6 */ crc00 = 0b00000000; /* set cr000 and cr010 to compare register */ cr000 = intervaltm00; /* set cycle initial value to cr000 */ toc00 = 0b00000111; /* invert on match with cr000, initial value l */ tmc00 = 0b00001100; /* clear & start on match between tm00 and cr000 */ ei(); while(1); /* loop as dummy here */ } /* timer 00 interrupt function */ void intervalint() { unsigned int work; /***************************************************/ /* */ /* define variables required for interrupt here */ /* */ /***************************************************/ work = ppgdata; if (work != 0) { cr000 = work; ppgdata = 0; if (work == 0xffff) { tmc00 = 0b00000000; /* stop timer */ } } /***********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /***********************************************************/ } 178 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.5.2 pulse width measurement by free-running counter and one capture register /******************************************************************************/ /* */ /* timer 00 operation sample */ /* pulse width measurement example by free-running and cr010 */ /* measurement results to be up to 16 bits and not checked for errors */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm010 intervalint rb2 unsigned int data[3]; /* data area */ void main(void) { unsigned int length; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; data[1] = 0; data[2] = 0; /* set port */ pm7.0 = 1; /* set p70 as input */ /* set interrupt */ tmmk010 = 0; /* cancel inttm010 interrupt mask */ /* set timer 00 */ prm00 = 0b00110010; /* both rising and falling edges for ti000 */ /* count clock is fx/2^6 */ crc00 = 0b00000100; /* set cr010 to capture register */ tmc00 = 0b00000100; /* start in free-run mode */ ei(); while(1){ /* dummy loop */ while(data[0] == 0); /* wait for measurement completion */ di(); /* disable interrupt for exclusive operation */ length = data[1]; /* read measurement results */ data[0] = 0; /* clear end flag */ ei(); /* exclusive operation completed */ } } /* timer 00 interrupt function */ void intervalint() { unsigned int work; /*****************************************************/ /* */ /* define variables required for interrupt here */ /* */ /*****************************************************/ work = cr010; /* read capture value */ data[1] = work - data[2]; /* calculate and update interval */ data[2] = work; /* update read value */ data[0] = 0xffff; /* set measurement completion flag*/ /***********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /***********************************************************/ } 179 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.5.3 two pulse widths measurement by free-running counter /******************************************************************************/ /* */ /* timer 00 operation sample */ /* two-pulse-width measurement sample by free-running */ /* measurement results to be up to 16 bits and not checked for errors */ /* result area at ti000 side */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* result area at ti010 side */ /* data[3]: end flag */ /* data[4]: measurement results (pulse width) */ /* data[5]: previous read value */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm000 intervalint rb2 #pragma interrupt inttm010 intervalint2 rb2 unsigned int data[6]; /* data area */ void main(void) { unsigned int length,length2; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; /* clear data area */ data[1] = 0; data[2] = 0; data[3] = 0; data[4] = 0; data[5] = 0; /* set port */ pm7.0 = 1; /* set p70 as input */ pm7.1 = 1; /* set p71 as input */ /* set interrupt */ tmmk010 = 0; /* cancel inttm010 interrupt mask */ tmmk000 = 0; /* cancel inttm000 interrupt mask */ /* set timer 00 */ prm00 = 0b11110010; /* both rising and falling edges */ /* count clock is fx/2^6 */ crc00 = 0b00000101; /* set cr000 and cr010 to capture register */ tmc00 = 0b00000100; /* start in free-run mode */ ei(); while(1){ /* dummy loop */ if(data[0] != 0) /* ti000 measurement completion check */ { tmmk010 = 1; /* inttm010 interrupt disabled for exclusive operation */ length = data[1]; /* read measurement results */ data[0] = 0; /* clear end flag */ tmmk010 = 0; /* exclusive operation completed */ } if(data[3] != 0) /* ti010 measurement completion check */ { tmmk000 = 1; /* inttm000 interrupt disabled for exclusive operation */ length2 = data[4]; /* read measurement results */ data[3] = 0; /* clear end flag */ tmmk000 = 0; /* exclusive operation completed */ } } } 180 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud /* inttm000 interrupt function */ void intervalint() { unsigned int work; /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ work = cr000; /* read capture value */ data[4] = work - data[5]; /* calculate and update interval */ data[5] = work; /* update read value */ data[3] = 0xffff; /* set measurement completion flag */ /********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /********************************************************/ } /* inttm010 interrupt function */ void intervalint2() { unsigned int work; /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ work = cr010; /* read capture value */ data[1] = work - data[2]; /* calculate and update interval */ data[2] = work; /* update read value */ data[0] = 0xffff; /* set measurement completion flag */ /********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /********************************************************/ } 181 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.5.4 pulse width measurement by restart /**************************************************************************/ /* */ /* timer 00 operation sample */ /* pulse width measurement example by restart */ /* measurement results up to 16 bits, not to be checked for errors */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* */ /**************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm010 intervalint rb2 unsigned int data[3]; /* data area */ void main(void) { unsigned int length; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; data[1] = 0; data[2] = 0; /* set port */ pm7.0 = 1; /* set p70 as input */ /* set interrupt */ tmmk010 = 0; /* cancel inttm010 interrupt mask */ /* set timer 00 */ prm00 = 0b00110010; /* both rising and falling edges */ /* count clock is fx/2^6 */ crc00 = 0b00000100; /* set cr010 to capture register */ tmc00 = 0b00001000; /* clear & start at ti000 valid edge */ ei(); while(1){ /* dummy loop */ if(data[0] != 0) /* wait for ti000 measurement completion */ { tmmk010 = 1; /* disable inttm010 for exclusive operation */ length = data[1]+data[2]; /* cycle calculation based on measurement results */ data[0] = 0; /* clear end flag */ tmmk010 = 0; /* exclusive operation completed */ } } } /* timer00 interrupt function */ void intervalint() { /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ data[2] = data[1]; /* update old data */ data[1] = cr010; /* update read value */ data[0] = 0xffff; /* set measurement completion flag*/ /********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /********************************************************/ } 182 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud 8.5.5 ppg output /******************************************************************************/ /* */ /* timer 00 ppg mode setting example */ /* cycle set to 130 as intervaltm00 */ /* active period set to 65 as active_time */ /* array ppgdata prepared as data area for rewriting */ /* [0]: active period (0000: no change, 0xffff: stop) */ /* [1]: cycle (0000: no change) */ /* ppgdata to be checked at every inttm000, and changed if required. */ /* therefore, if change is required, set the change data in ppgdata. */ /* when changed, ppgdata cleared to 0000. */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm00 130 /* cycle data to be set to cr000 */ #define active_time 65 /* initial value data of cr010 */ #pragma interrupt inttm000 ppgint rb2 unsigned int ppgdata[2]; /* data area to be set to timer 00 */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ ppgdata[0] = 0; ppgdata[1] = 0; /* set port */ p7 = 0b11111110; /* clear p70 */ pm7.0 = 0; /* set p70 to output */ /* set interrupt */ tmmk000 = 0; /* cancel inttm000 interrupt mask */ /* set timer 00 */ prm00 = 0b00000010; /* count clock is fx/2^6 */ crc00 = 0b00000000; /* set cr000 and cr010 to compare register */ cr000 = intervaltm00; /* set initial value of cycle */ cr010 = active_time; /* set initial value of active period */ toc00 = 0b00010111; /* inverted on match between cr000 and cr010, initial value l */ tmc00 = 0b00001100; /* clear & start on match between tm00 and cr000 */ ei(); while(1); } /* timer 00 interrupt function */ void ppgint() { unsigned int work; work = ppgdata[0]; if (work != 0) { cr010 = work; ppgdata[0] = 0; if (work == 0xffff) { tmc00 = 0b00000000; /* stop timer */ } } work = ppgdata[1]; if (work != 0) { cr000 = work; ppgdata[1]=0; } } 183 chapter 8 16-bit timer/event counters 00, 01 user? manual u14260ej3v1ud 8.6 cautions for 16-bit timer/event counters 00, 01 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 0n (tm0n) is started asynchronously to the count clock. figure 8-37. start timing of 16-bit timer counter 0n (tm0n) (2) 16-bit timer capture/compare register setting in the clear & start mode entered on a match between tm0n and cr00n, set a value other than 0000h to 16- bit timer capture/compare register 00n (cr00n). this means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 0n is used as an external event counter. (3) capture register data retention timing the values of 16-bit timer capture/compare registers 00n and 01n (cr00n and cr01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped. (4) valid edge setting set the valid edge of the ti00n pin after setting bits 2 and 3 (tmc0n2 and tmc0n3) of 16-bit timer mode control register 0n (tmc0n) to 0, 0, respectively, and then stopping the timer operation. the valid edge is set by bits 4 and 5 (es00n and es01n) of prescaler mode register 0n (prm0n). remark n = 0, 1 tm0n count value 0000h 0001h 0002h 0004h count clock timer start 0003h 184 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (5) operation of ovf0n flag <1> the ovf0n flag is also set to 1 in the following case. either of the clear & start mode entered on a match between tm0n and cr00n, clear & start at the valid edge of the ti00n pin, or free-running mode is selected. cr00n is set to ffffh. when tm0n is counted up from ffffh to 0000h. figure 8-38. operation timing of ovf0n flag count clock cr00n tm0n ovf0n inttm00n ffffh fffeh ffffh 0000h 0001h <2> even if the ovf0n flag is cleared before the next count clock is counted (before tm0n becomes 0001h) after the occurrence of a tm0n overflow, the ovf0 flag is reset newly and clear is disabled. (6) conflicting operations <1> when the 16-bit timer capture/compare register (cr00n/cr01n) is used as a compare register, if the write period and the match timing of 16-bit timer counter 0n (tm0n) conflict, match determination is not successfully done. do not perform a write operation of cr00n/cr01n near the match timing. <2> if the read period and capture trigger input conflict when cr00n/cr01n is used as a capture register, capture trigger input has priority. the data read from cr00n/cr01n is undefined. remark n = 0, 1 185 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud figure 8-39. capture register data retention timing (7) timer operation <1> even if 16-bit timer counter 0n (tm0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (cr01n). <2> regardless of the cpu s operation mode, when the timer stops, the signals input to pins ti00n/ti01n are not acknowledged. (8) capture operation <1> if the ti00n pin is specified as the valid edge of the count clock, a capture operation by the capture register specified as the trigger for the ti00n pin is not possible. <2> if both the rising and falling edges are selected as the valid edges of the ti00n pin, capture is not performed. <3> to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0n (prm0n). <4> the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0nn), however, occurs at the rise of the next count clock. (9) compare operation <1> when the 16-bit timer capture/compare register (cr00n/cr01n) is overwritten during timer operation, match interrupt may be generated or the clear operation may not be performed normally if that value is close to or large than the timer value. <2> the capture operation may not be performed for cr00n/cr01n set in compare mode even if a capture trigger is input. remark n = 0, 1 count clock tm0n count value edge input inttm01n capture read signal cr01n capture value n n + 1 n + 2 m m + 1 m + 2 x n + 1 m + 1 read value not guaranteed though capture operation performed capture 186 chapter 8 16-bit timer/event counters 00, 01 user s manual u14260ej3v1ud (10) edge detection <1> if the ti00n pin or the ti01n pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge for the ti00n pin or ti01n pin to enable 16-bit timer counter 0n (tm0n) operation, a rising edge is detected immediately. be careful when pulling up the ti00n pin or the ti01n pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to eliminate noise differs when the valid edge of the ti00n pin is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x /2 3 , and in the latter case the count clock is selected by prescaler mode register 0n (prm0n). the capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. (11) stop mode or main system clock stop mode setting except when the ti00n, ti01n pin input is selected, stop the timer operation before setting stop mode or main system clock stop mode; otherwise the timer may malfunction when the main system clock starts. remark n = 0, 1 187 user? manual u14260ej3v1ud chapter 9 8-bit timer/event counters 50, 51 9.1 functions of 8-bit timer/event counters 50, 51 8-bit timer/event counters 50, 51 (tm50, tm51) have the following two modes. (1) mode using 8-bit timer/event counters 50, 51 alone (discrete mode) the timer operates as 8-bit timer/event counter 50 or 51. it has the following functions. <1> interval timer interrupt requests are generated at the preset interval. number of counts: 1 to 256 <2> external event counter the number of pulses with high/low level widths of the signal input externally can be measured. <3> square-wave output a square wave with an arbitrary frequency can be output. cycle: (1 2 to 256 2) cycles of count clock <4> pwm output a pulse with an arbitrary duty ratio can be output. cycle: count clock 256 duty ratio: set value of compare register/256 (2) mode using cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by combining two 8-bit timer/event counters. it has the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square-wave output with 16-bit resolution figures 9-1 and 9-2 show block diagrams of 8-bit timer/event counters 50 and 51. 188 chapter 9 8-bit timer/event counters 50, 51 user? manual u14260ej3v1ud figure 9-1. block diagram of 8-bit timer/event counter 50 figure 9-2. block diagram of 8-bit timer/event counter 51 notes 1. the respective combinations, ti50 and to50 pins, and ti51 and to51 pins, cannot be used at the same time. 2. timer output f/f 3. pwm output f/f output latch (p72) pm72 to50/ti50/ p72 note 1 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p72 note 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 note 2 note 3 selector 8-bit timer counter 50 (tm50) selector output latch (p73) pm73 to51/ti51/ p73 note 1 internal bus ti51/to51/p73 note 1 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r q r inv selector inttm51 selector selector selector 8-bit timer compare register 51 (cr51) 8-bit timer counter 51 (tm51) s f x /2 11 note 2 note 3 189 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.2 configuration of 8-bit timer/event counters 50, 51 8-bit timer/event counters 50, 51 consist of the following hardware. table 9-1. configuration of 8-bit timer/event counters 50, 51 item configuration timer counter 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) port register 7 (p7) (1) 8-bit timer counter 5n (tm5n: n = 0, 1) tm5n is an 8-bit read-only register that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. figure 9-3. format of 8-bit timer counter 5n (tm5n) when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction. however, since they are connected by an internal 8-bit bus, tm50 and tm51 are read separately twice in that order. thus, take reading during the count change into consideration and compare them by reading twice. when the count value is read during operation, the count clock input is temporarily stopped note , and then the count value is read. in the following situations, count value is set to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in the clear & start mode entered on a match between tm5n and cr5n. note an error may occur in the count. select a count clock that has a high/low level longer than two cycles of the cpu clock. caution in cascade connection mode, the count value is reset to 0000h when tce50 of the lowest timer is cleared. remark n = 0, 1 symbol tm5n (n = 0, 1) address: ff12h (tm50), ff13h (tm51) after reset: 00h r 190 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud (2) 8-bit timer compare register 5n (cr5n: n = 0, 1) when cr5n is used as a compare register in other than pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter (tm5n) count value, and an interrupt request (inttm5n) is generated if they match. in pwm mode, the to5n pin goes to the active level by the overflow of tm5n. when the values of tm5n and cr5n match, the to5n pin goes to the inactive level. it is possible to rewrite the value of cr5n within 00h to ffh during a count operation. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, cr50 and cr51 operate as a 16-bit compare register. this register compares the count value with the register value, and if the values match, an interrupt request (inttm50) is generated. the inttm51 interrupt request is also generated at this time. thus, mask the inttm51 interrupt request. cr5n is set by an 8-bit memory manipulation instruction. cr5n is undefined when reset is input. figure 9-4. format of 8-bit timer compare register 5n (cr5n) cautions 1. cr5n can be rewritten in pwm mode only once per cycle. 2. in cascade connection mode, stop the timer operation before setting data. remark n = 0, 1 symbol cr5n (n = 0, 1) address: ff10h (cr50), ff11h (cr51) after reset: undefined r/w 191 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.3 registers to control 8-bit timer/event counters 50, 51 the following four types of registers are used to control 8-bit timer/event counters 50, 51. timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) port register 7 (p7) remark n = 0, 1 (1) timer clock select register 5n (tcl5n: n = 0, 1) this register sets the count clock of 8-bit timer/event counter 5n and the valid edge of ti50, ti51 input. tcl5n is set by an 8-bit memory manipulation instruction. reset input clears tcl5n to 00h. figure 9-5. format of timer clock select register 50 (tcl50) address: ff71h after reset: 00h r/w symbol 76543210 tcl50 00000 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection f x = 8.38 mhz f x = 12 mhz note 0 0 0 ti50 falling edge ?? 0 0 1 ti50 rising edge ?? 010f x 8.38 mhz 12 mhz 011f x /2 2 2.09 mhz 3 mhz 100f x /2 4 523 khz 750 khz 101f x /2 6 131 khz 187 khz 110f x /2 8 32.7 khz 46.8 khz 111f x /2 10 8.18 khz 11.7 khz note expanded-specification products of pd780078 subseries only. cautions 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. when cascade connection is used, only tcl50 is valid for count clock setting. 2. f x : main system clock oscillation frequency 192 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-6. format of timer clock select register 51 (tcl51) address: ff79h after reset: 00h r/w symbol 76543210 tcl51 00000 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection f x = 8.38 mhz f x = 12 mhz note 0 0 0 ti51 falling edge ?? 0 0 1 ti51 rising edge ?? 010f x /2 4.19 mhz 6 mhz 011f x /2 3 1.04 mhz 1.5 mhz 100f x /2 5 261 khz 375 khz 101f x /2 7 65.4 khz 93.7 khz 110f x /2 9 16.3 khz 23.4 khz 111f x /2 11 4.09 khz 5.85 khz note expanded-specification products of pd780078 subseries only. cautions 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remarks 1. when cascade connection is used, only tcl50 is valid for count clock setting. 2. f x : main system clock oscillation frequency (2) 8-bit timer mode control register 5n (tmc5n: n = 0, 1) tmc5n is a register that makes the following six settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> discrete mode/cascade connection mode selection (tmc51 only) <4> timer output f/f (flip-flop) status setting <5> active level selection in timer f/f control or pwm (free-running) mode <6> timer output control tmc5n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc5n to 00h. 193 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-7. format of 8-bit timer mode control register 50 (tmc50) address: ff70h after reset: 00h r/w symbol 76543210 tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (prescaler disabled) 1 count operation start tmc506 tm50 operating mode selection 0 clear and start mode by match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tmc501 in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe50 timer output control 0 output disabled (port mode) 1 output enabled cautions 1. the settings of lvs50 and lvr50 are valid in modes other than the pwm mode. 2. do not set <1> to <3> below at the same time. set as follows. <1> tmc501 and tmc506: setting of operation mode <2> set toe50 for output enable: timer output enable <3> set tce50 set lvs50 and lvr50 before <3>. 3. stop operation before rewriting tmc506. remarks 1. in pwm mode, pwm output will be inactive because tce50 = 0. 2. if lvs50 and lvr50 are read, 0 is read. 3. the values of the tmc506, lvs50, lvr50, tmc501, and toe50 bits are reflected to the to50 output regardless of the value of tce50. 194 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-8. format of 8-bit timer mode control register 51 (tmc51) address: ff78h after reset: 00h r/w symbol 76543210 tmc51 tce51 tmc516 0 tmc514 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (prescaler disabled) 1 count operation start tmc516 tm51 operating mode selection 0 clear and start mode by match between tm51 and cr51 1 pwm (free-running) mode tmc514 discrete mode/cascade connection mode selection 0 discrete mode 1 cascade connection mode (tm50: lower timer, tm51: higher timer) lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tmc511 in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe51 timer output control 0 output disabled (port mode) 1 output enabled cautions 1. the settings of lvs51 and lvr51 are valid in modes other than the pwm mode. 2. do not set <1> to <3> below at the same time. set as follows. <1> tmc511, tmc516, and tmc514: setting of operation mode <2> set toe51 for output enable: timer output enable <3> set tce51 set lvs51 and lvr51 before <3>. 3. stop operation before rewriting tmc516. remarks 1. in pwm mode, pwm output will be inactive because tce51 = 0. 2. if lvs51 and lvr51 are read, 0 is read. 3. the values of the tmc516, lvs51, lvr51, tmc514, tmc511, and toe51 bits are reflected to the to51 output regardless of the value of tce51. 195 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud (3) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p72/to50/ti50 and p73/ti51/to51 pins for timer output, set pm72 and pm73, and the output latches of p72 and p73 to 0. when using the p72/to50/ti50 and p73/ti51/to51 pins for timer input, set pm72 and pm73 to 1. at this time, the output latches of p72 and p73 can be either 0 or 1. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 9-9. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) 196 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.4 operation of 8-bit timer/event counters 50, 51 9.4.1 8-bit interval timer operation the 8-bit timer/event counters operate as interval timers that generate interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) matches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). setting <1> set each register. tcl5n: select count clock. cr5n: compare value tmc5n: count operation stop, clear & start mode on match between tm5n and cr5n. (tmc5n = 0000 0b = don t care) <2> after tce5n = 1 is set, count operation starts. <3> if the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. remark n = 0, 1 figure 9-10. interval timer operation timing (1/3) (a) basic operation remarks 1. interval time = (n + 1) t n = 00h to ffh 2. n = 0, 1 t count clock tm5n count value cr5n tce5n inttm5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time 197 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-10. interval timer operation timing (2/3) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1 198 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-10. interval timer operation timing (3/3) (d) operated by cr5n transition (m < n) count clock tm5n cr5n tce5n inttm5n 00h n n m n ffh 00h m 00h m cr5n transition tm5n overflows since m < n h (e) operated by cr5n transition (m > n) count clock tm5n cr5n tce5n inttm5n n 1n n 00h 01h n m 1 m 00h 01h m cr5n transition h remark n = 0, 1 199 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to ti5n using 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock select register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit timer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n count value matches the value of cr5n, inttm5n is generated. setting <1> set each register. set the port mode register (pm72 or pm73) note to 1 tcl5n: edge selection of ti5n input rising edge of ti5n tcl5n = 00h falling edge of ti5n tcl5n = 01h cr5n: compare value tmc5n: count operation stop, clear & start mode on match between tm5n and cr5n, timer f/f inverted operation disable, timer output disable (tmc5n = 0000 00b, = don t care) <2> when tce5n = 1 is set, the number of pulses input from ti5n is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> each time the values of tm5n and cr5n match, inttm5n is generated. note 8-bit timer/event counter 50: pm72 8-bit timer/event counter 51: pm73 figure 9-11. external event counter operation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n count start remarks 1. n = 00h to ffh 2. n = 0, 1 200 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.4.3 square-wave output (8-bit resolution) operation a square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is reversed at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. set port output latches (p72, p73) note and port mode registers (pm72, pm73) note to 0. tcl5n: select count clock cr5n: compare value tmc5n: count operation stop, clear & start mode on match between tm5n and cr5n lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f reverse enable timer output enable toe5n = 1 (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> timer output f/f is reversed by match between tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> timer output f/f is reversed at the same interval and a square wave is output from to5n. the frequency is as follows. frequency = 1/2t (n + 1) (n = 00h to ffh) note 8-bit timer/event counter 50: p72, pm72 8-bit timer/event counter 51: p73, pm73 remark n = 0, 1 201 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-12. square-wave output operation timing count clock tm5n count value cr5n to5n note count start 00h 01h 02h n 1n 00h 01h 02h n 1n 00h n t note the to5n output initial value can be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). remarks 1. n = 00h to ffh 2. n = 0, 1 9.4.4 8-bit pwm output operation the 8-bit timer/event counter operates as pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty ratio pulse is determined by the value set to 8-bit timer compare register 5n (cr5n). set the active level width of the pwm pulse to cr5n. the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). pwm output enable/disable can be selected with bit 0 (toe5n) of tmc5n. caution cr5n can be rewritten in pwm mode only once per cycle. remark n = 0, 1 202 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud (1) pwm output basic operation setting <1> set each register. set port output latches (p72, p73) note and port mode registers (pm72, pm73) note to 0. tcl5n: count clock selection cr5n: compare value tmc5n: count operation stop, pwm mode selection, timer output f/f not changed tmc5n1 active level selection 0 active high 1 active low timer output enabled (tmc5n = 01000001b or 01000011b) <2> when tce5n = 1 is set, the count operation is started. to stop the count operation, set tce5n to 0. note 8-bit timer/event counter 50: p72, pm72 8-bit timer/event counter 51: p73, pm73 pwm output operation <1> pwm output (output from to5n) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> when cr5n matches the count value, the inactive level is output. the inactive level is output until an overflow occurs again. <4> operations <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped by setting tce5n = 0, pwm output becomes the inactive level. for details of timing, see figures 9-13 and 9-14 . the cycle, active-level width, and duty are as follows. cycle = 2 8 t active-level width = nt duty = n/2 8 (n = 00h to ffh) remark n = 0, 1 203 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud figure 9-13. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h n <2> active level active level <3> inactive level <5> <1> t (b) cr5n = 0 count clock tm5n cr5n tce5n inttm5n to5n l inactive level inactive level 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h 00h n+2 t (c) cr5n = ffh tm5n count clock cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n+1 ffh 00h 01h 02h m 00h ffh n+2 inactive level active level inactive level active level inactive level t remarks 1. <1> to <3> and <5> in figure 9-13 (a) correspond to <1> to <3> and <5> in pwm output operation in 9.4.4 (1) pwm output basic operation . 2. n = 0, 1 204 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud (2) operation with cr5n changed figure 9-14. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n between <1> and <2> in figure 9-14, the value read differs from the actual value (read value: m, actual value of cr5n: n). remark n = 0, 1 205 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.4.5 interval timer (16-bit) operations when bit 4 (tmc514) of 8-bit timer mode control register 51 (tmc51) is set to 1, the 16-bit resolution timer/counter mode is entered. the 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit timer compare registers (cr50, cr51). setting <1> set each register. tcl50: select count clock for tm50. cascade-connected tm51 need not be selected. cr50, cr51: compare value (each value can be set to 00h to ffh) tmc50, tmc51: select the clear & start mode entered on a match between tm50 and cr50 (tm51 and cr51). tm50 tmc50 = 0000 0b : don t care tm51 tmc51 = 0001 0b : don t care <2> when tmc51 is set to tce51 = 1 and then tmc50 is set to tce50 = 1, the count operation starts. <3> when the values of tm50 and cr50 of the cascade-connected timer match, inttm50 of tm50 is generated (tm50 and tm51 are cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. cautions 1. stop the timer operation without fail before setting the compare registers (cr50, cr51). 2. inttm51 of tm51 is generated when the tm51 count value matches cr51, even if cascade connection is used. be sure to mask tm51 to disable interrupts. 3. set tce50 and tce51 in order of tm51 then tm50. 4. count restart/stop can only be controlled by setting tce50 of tm50 to 1/0. figure 9-15 shows an example of 16-bit resolution cascade connection mode timing. figure 9-15. 16-bit resolution cascade connection mode count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 operation enable count start interval time 00h 01h n n+1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h m 1 m 00h b 00h n m interrupt request generation, counter clear operation stop 206 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.5 program list caution the following sample program is shown as an example to describe the operation of semiconductor products and their applications. therefore, when applying the following information to your devices, design the devices after performing evaluation under your own responsibility. 9.5.1 interval timer (8-bit) /*************************************************************************************/ /* */ /* timer 50 operation sample */ /* interval timer setting example (frequency change by interrupt processing) */ /* data[0]: data set flag (value changed when other than 00) */ /* data[1]: set data */ /* */ /*************************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm50 intervalint rb2 unsigned char data[2]; /* data area */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; /* clear data area */ data[1] = 0; /* set port */ p7 = 0b11111011; /* when using to50 */ pm7.2 = 0; /* set p72 to output */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ /* set timer 50 */ tmc50 = 0b00000111; /* clear & start mode, initial value l */ tcl50 = 0b00000101; /* both rising and falling edges */ /* count clock is fx/2^6 */ cr50 = 131; /* set interval to 1 ms as initial value */ tce50 = 1; /* timer start */ ei(); while(1); /* dummy loop */ } /* inttm50 interrupt function */ void intervalint() { if(data[0] != 0) { cr50 = data[1]; /* set new set value */ data[0] = 0; /* clear request flag */ } } 207 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.5.2 external event counter /***************************************************************/ /* */ /* timer 50 operation sample */ /* event counter setting example */ /* data: count up flag */ /* */ /***************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm50 intervalint rb2 unsigned char data; /* data area */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ data = 0; /* clear data area */ /* set port */ pm7.2 = 1; /* set p72 to input */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ /* set timer 50 */ tmc50 = 0b00000000; /* clear & start mode */ tcl50 = 0b00000001; /* specify rising edge of ti50 */ cr50 = 0x10; /* set n = 16 as initial value */ tce50 = 1; /* timer start */ ei(); /*************************************************************/ /* */ /* describe the processing to be executed */ /* */ /*************************************************************/ while(data == 0); /* wait for count up */ /*************************************************************/ /* */ /* describe the processing after count up below */ /* */ /*************************************************************/ } /* inttm50 interrupt function */ void intervalint() { data = 0xff; /* set count up flag */ tce50 = 0; /* timer stop */ } 208 chapter 9 8-bit timer/event counters 50, 51 user s manual u14260ej3v1ud 9.5.3 interval timer (16-bit) /***************************************************************/ /* */ /* timer 5 operation sample */ /* cascade connection setting example */ /* */ /***************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm5 130 /* cycle data to be set to cr */ #pragma interrupt inttm50 ppgint rb2 unsigned char ppgdata[2]; /* data area to be set to timer 5 */ void main(void) { int interval; interval = intervaltm5; pcc = 0x0; /* select high-speed operation mode */ ppgdata[0] = 0; /* clear cr50 data */ ppgdata[1] = 0; /* clear cr51 data */ /* set port */ p7 = 0b11111011; /* clear p72 */ pm7.2 = 0; /* set p72 to output */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ tmmk51 = 1; /* set inttm51 interrupt mask */ /* set timer 5 */ tcl50 = 0b00000101; /* count clock is fx/2^6 */ cr50 = interval & 0xff; /* set lower compare register to cr50 */ cr51 = interval >> 8; /* set higher compare register to cr51 */ tmc50 = 0b00000111; /* inverted on match, initial value l */ tmc51 = 0b00010000; /* cascade mode */ tce51 = 1; tce50 = 1; /* timer starts */ ei(); while(1); } /* timer 5 interrupt function */ void ppgint() { unsigned int work; work = ppgdata[0]+ppgdata[1]*0x100; if (work != 0) { tce50 =0; cr51 = work >> 8; cr50 = work & 0xff; ppgdata[0] = 0; ppgdata[1] = 0; if (work != 0xffff) { tce50 = 1; /* timer resumes */ } } } 209 chapter 9 8-bit timer/event counters 50, 51 user? manual u14260ej3v1ud 9.6 cautions for 8-bit timer/event counters 50, 51 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counter 5n (tm5n) is started asynchronously to the count pulse. figure 9-16. start timing of 8-bit timer counter 5n (tm5n) count pulse tm5n count value 00h 01h 02h 03h 04h timer start (2) setting stop mode or main system clock stop mode except when ti5n input is selected, always set tce5n = 0 before setting the stop mode or main system clock stop mode. the timer may malfunction when the main system clock starts oscillating. (3) tm5n (n = 0, 1) reading during timer operation when reading tm5n during operation, the count clock stops temporarily, so select a count clock with a high/low- level waveform longer than two cycles of the cpu clock. for example, in the case where the cpu clock (f cpu ) is fx, when the selected count clock is fx/4 or below, it can be read. remark n = 0, 1 210 user? manual u14260ej3v1ud chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at 2 14 /f w second or 2 5 /f w second intervals. (2) interval timer interrupt requests (intwti) are generated at the preset time interval. for the interval time, refer to table 10-2 . the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. watch timer block diagram remark f w : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f wx : f w or f w /2 9 f x /2 7 f xt selector selector f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm3 wtm0 watch timer operation mode register (wtm) internal bus selector f wx 211 chapter 10 watch timer user s manual u14260ej3v1ud 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-1. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer operation mode register (wtm) 10.3 register to control watch timer the watch timer is controlled by the watch timer operation mode register (wtm). watch timer operation mode register (wtm) this register sets the watch timer count clock, enables/disables operation, sets the prescaler interval time, controls the 5-bit counter operation, and sets the watch timer interrupt request time. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h. 212 chapter 10 watch timer user s manual u14260ej3v1ud figure 10-2. format of watch timer operation mode register (wtm) address: ff41h after reset: 00h r/w symbol 76543210 wtm wtm7 wtm6 wtm5 wtm4 wtm3 0 wtm1 wtm0 wtm7 watch timer count clock selection 0f x /2 7 (65.4 khz: f x = 8.38 mhz, 93.7 khz: f x = 12 mhz note ) 1f xt (32.768 khz: f xt = 32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0002 4 /f w 0012 5 /f w 0102 6 /f w 0112 7 /f w 1002 8 /f w 1012 9 /f w other than above setting prohibited wtm3 interrupt request time of watch timer 02 14 /f w 12 5 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stopped (both prescaler and timer cleared) 1 operation enabled note expanded-specification products of pd780078 subseries only. caution do not change the count clock, interval time, and interrupt request time (by using bits 3 to 7 (wtm3 to wtm7) of wtm) while the watch timer is operating. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 213 chapter 10 watch timer user s manual u14260ej3v1ud 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt request (intwt) at specific time intervals (2 14 /f w seconds or 2 5 /f w seconds) by using the main system clock or subsystem clock. the interrupt request is generated at the following time intervals (where wtm3 = 0). if main system clock (8.38 mhz) is selected: 0.25 seconds if subsystem clock (32.768 khz) is selected: 0.5 seconds when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer operation mode register (wtm) are set to 1, the count operation starts, and when these bits are set to 0, the 5-bit counter is cleared and the count operation stops. when the interval timer is simultaneously operated, a zero-second start can be achieved for the watch timer by setting wtm1 to 1 after clearing it to 0. in this case, however, the 9-bit prescaler is not cleared. therefore, an error up to 2 9 /f w seconds occurs in the first overflow (intwt) after the zero-second start. remark f w : watch timer clock frequency (f x /2 7 or f xt ) 10.4.2 interval timer operation the watch timer operates as interval timer that generates interrupt requests (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer operation mode register (wtm). when bit 0 (wtm0) of wtm is set to 1, the count operation starts. when this bit is cleared to 0, the count operation stops. table 10-2. interval timer interval time wtm6 wtm5 wtm4 interval when operated at when operated at when operated at when operated at time f x = 12 mhz note f x = 8.38 mhz f x = 4.19 mhz f xt = 32.768 khz 0002 4 /f w 170 s 244 s 488 s 488 s 0012 5 /f w 341 s 488 s 977 s 976 s 0102 6 /f w 682 s 977 s 1.95 ms 1.95 ms 0112 7 /f w 1.36 ms 1.95 ms 3.91 ms 3.90 ms 1002 8 /f w 2.73 ms 3.91 ms 7.82 ms 7.81 ms 1012 9 /f w 5.46 ms 7.82 ms 15.6 ms 15.6 ms other than above setting prohibited note expanded-specification products of pd780078 subseries only. remark f w : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 214 chapter 10 watch timer user s manual u14260ej3v1ud figure 10-3. operation timing of watch timer/interval timer remark f w : watch timer clock frequency (f x /2 7 or f xt ) n: the number of interval timer operations 10.5 cautions for watch timer when operation of the watch timer and 5-bit counter is enabled by the watch timer operation mode register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the interval until the first interrupt request (intwt) is generated after the register is set does not exactly match the specification made with bit 3 (wtm3) of wtm. this is because there is a delay of one 11-bit prescaler output cycle until the 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. figure 10-4. example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0h start overflow overflow 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (2 14 /f w or 2 5 /f w sec.) interval time (t) t interrupt time of watch timer (2 14 /f w or 2 5 /f w sec.) n x t n x t 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt 215 user? manual u14260ej3v1ud chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. (1) watchdog timer the watchdog timer detects a program loop. upon detection of a program loop, a non-maskable interrupt request or reset can be generated. for the loop detection time, refer to table 11-2 . (2) interval timer interrupt requests are generated at the preset time intervals. for the interval time, refer to table 11-3 . caution select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (wdtm). (the watchdog timer and the interval timer cannot be used simultaneously.) figure 11-1 shows a block diagram of the watchdog timer. figure 11-1. watchdog timer block diagram wdt mode signal watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) f x /2 8 f x run intwdt reset 3 wdcs2 wdcs1 wdcs0 run wdtm4 wdtm3 clock input controller divider circuit divided clock selector output controller division mode selector internal bus 216 chapter 11 watchdog timer user s manual u14260ej3v1ud 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-1. watchdog timer configuration item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 11.3 registers to control watchdog timer the following two registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the overflow time of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input clears wdcs to 00h. figure 11-2. format of watchdog timer clock select register (wdcs) address: ff42h after reset: 00h r/w symbol 76543210 wdcs 00000 wdcs2 wdcs1 wdcs0 wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer f x = 8.38 mhz f x = 12 mhz note 0002 12 /f x 488 s 341 s 0012 13 /f x 977 s 682 s 0102 14 /f x 1.95 ms 1.36 ms 0112 15 /f x 3.91 ms 2.73 ms 1002 16 /f x 7.82 ms 5.46 ms 1012 17 /f x 15.6 ms 10.9 ms 1102 18 /f x 31.2 ms 21.8 ms 1112 20 /f x 125 ms 87.3 ms note expanded-specification products of pd780078 subseries only. remark f x : main system clock oscillation frequency 217 chapter 11 watchdog timer user s manual u14260ej3v1ud (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 11-3. format of watchdog timer mode register (wdtm) address: fff9h after reset: 00h r/w symbol 76543210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run watchdog timer operation mode selection note 1 0 count stop 1 counter is cleared and counting starts wdtm4 wdtm3 watchdog timer operation mode selection note 2 0 interval timer mode note 3 (maskable interrupt request occurs upon generation of overflow) 1 0 watchdog timer mode 1 (non-maskable interrupt request occurs upon generation of overflow) 1 1 watchdog timer mode 2 (reset operation is activated upon generation of overflow) notes 1. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. caution when run is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 2 8 /f x seconds shorter than the time set by the watchdog timer clock select register (wdcs). remark : don t care 218 chapter 11 watchdog timer user s manual u14260ej3v1ud 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect a program loop. the loop detection time interval is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). the watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set loop time interval. the watchdog timer can be cleared and counting started by setting run to 1. if run is not set to 1 and the loop detection time is exceeded, system reset or a non-maskable interrupt request is generated according to the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual loop detection time may be shorter than the set time by up to 2 8 /f x seconds. 2. when the subsystem clock is selected for the cpu clock, the watchdog timer count operation is stopped. table 11-2. watchdog timer loop detection time loop detection time when operated at when operated at f x = 8.38 mhz f x = 12 mhz note 2 12 /f x 488 s 341 s 2 13 /f x 977 s 682 s 2 14 /f x 1.95 ms 1.36 ms 2 15 /f x 3.91 ms 2.73 ms 2 16 /f x 7.82 ms 5.46 ms 2 17 /f x 15.6 ms 10.9 ms 2 18 /f x 31.2 ms 21.8 ms 2 20 /f x 125 ms 87.3 ms note expanded-specification products of pd780078 subseries only. remark f x : main system clock oscillation frequency 219 chapter 11 watchdog timer user s manual u14260ej3v1ud 11.4.2 interval timer operation the watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 0. the interval time of the interval timer is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). when bit 7 (run) of wdtm is set to 1, the watchdog timer operates as an interval timer. when the watchdog timer operates as an interval timer, the interrupt mask flag (wdtmk) and priority specification flag (wdtpr) are validated and the maskable interrupt request (intwdt) can be generated. among the maskable interrupts, intwdt has the highest priority at default. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (this selects the watchdog timer mode), the interval timer mode is not set unless reset is input. 2. the interval time just after setting wdtm may be shorter than the set time by up to 2 8 /f x seconds. 3. when the subsystem clock is selected for the cpu clock, the watchdog timer count operation is stopped. table 11-3. interval timer interval time interval time when operated at when operated at f x = 8.38 mhz f x = 12 mhz note 2 12 /f x 488 s 341 s 2 13 /f x 977 s 682 s 2 14 /f x 1.95 ms 1.36 ms 2 15 /f x 3.91 ms 2.73 ms 2 16 /f x 7.82 ms 5.46 ms 2 17 /f x 15.6 ms 10.9 ms 2 18 /f x 31.2 ms 21.8 ms 2 20 /f x 125 ms 87.3 ms note expanded-specification products of pd780078 subseries only. remark f x : main system clock oscillation frequency 220 user? manual u14260ej3v1ud chapter 12 clock output/buzzer output controller 12.1 clock output/buzzer output controller functions clock output is used for carrier output during remote controlled transmission and clock output for supply to peripheral ics. the clock selected by the clock output select register (cks) is output. in addition, buzzer output is used for square-wave output of the buzzer frequency selected by cks. figure 12-1 shows the block diagram of the clock output/buzzer output controller. figure 12-1. block diagram of clock output/buzzer output controller f x f x /2 10 to f x /2 13 f x to f x /2 7 f xt bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/ti011/ p74 buz/ti001 / to01/p75 bcs0, bcs1 ccs3 ccs2 ccs1 ccs0 pm75 pm74 clock controller output latch (p75) output latch (p74) internal bus selector clock output select register (cks) selector prescaler 221 chapter 12 clock output/buzzer output controller user s manual u14260ej3v1ud 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller consists of the following hardware. table 12-1. configuration of clock output/buzzer output controller item configuration control registers clock output select register (cks) port mode register (pm7) port register 7 (p7) 12.3 registers to control clock output/buzzer output controller the following three registers are used to control the clock output/buzzer output controller. clock output select register (cks) port mode register (pm7) port register 7 (p7) (1) clock output select register (cks) this register sets output enable/disable for clock output (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears cks to 00h. 222 chapter 12 clock output/buzzer output controller user s manual u14260ej3v1ud figure 12-2. format of clock output select register (cks) address: ff40h after reset: 00h r/w symbol 76543210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 stop clock divider operation. buz fixed to low level. 1 enable clock divider operation. buz output enabled. bcs1 bcs0 buz output clock selection f x = 8.38 mhz f x = 12 mhz note 00f x /2 10 8.18 khz 11.7 khz 01f x /2 11 4.09 khz 5.85 khz 10f x /2 12 2.04 khz 2.92 khz 11f x /2 13 1.02 khz 1.46 khz cloe pcl output enable/disable specification 0 stop clock divider operation. pcl fixed to low level. 1 enable clock divider operation. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection f x = 8.38 mhz f x = 12 mhz note 0000f x 8.38 mhz 12 mhz 0001f x /2 4.19 mhz 6 mhz 0010f x /2 2 2.09 mhz 3 mhz 0011f x /2 3 1.04 mhz 1.5 mhz 0100f x /2 4 523 khz 750 khz 0101f x /2 5 261 khz 375 khz 0110f x /2 6 130 khz 187 khz 0111f x /2 7 65.4 khz 93.7 khz 1000f xt (32.768 khz) other than above setting prohibited note expanded-specification products of pd780078 subseries only. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f xt = 32.768 khz. 223 chapter 12 clock output/buzzer output controller user s manual u14260ej3v1ud (2) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p74/pcl/ti011 pin for clock output and the p75/buz/ti001/to01 pin for buzzer output, set pm74 and pm75, and the output latches of p74 and p75 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 12-3. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) 224 chapter 12 clock output/buzzer output controller user s manual u14260ej3v1ud 12.4 operation of clock output/buzzer output controller 12.4.1 operation as clock output the clock pulse is output using the following procedure. <1> select the clock pulse output frequency using bits 0 to 3 (ccs0 to ccs3) of the clock output select register (cks) (clock pulse output in disabled state). <2> set bit 4 (cloe) of cks to 1, and enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/ disable switching of the clock output. as shown in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing the high level of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output using the following procedure. <1> select the buzzer output frequency using bits 5 and 6 (bcs0, bcs1) of the clock output select register (cks) (buzzer output in disabled state). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output. 225 user? manual u14260ej3v1ud chapter 13 a/d converter 13.1 a/d converter functions the a/d converter is a 10-bit resolution converter that converts analog inputs into digital signals. it can control up to 8 analog input channels (ani0 to ani7). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 0 (adm0). select one channel for analog input from ani0 to ani7 to start a/d conversion. in the case of hardware start, the a/d converter stops when a/d conversion is completed, and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time an a/d conversion operation ends, an interrupt request (intad0) is generated. figure 13-1. block diagram of 10-bit a/d converter note the valid edge of an external interrupt is specified by bit 3 of the egp and egn registers (see figure 19- 5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) ). sample & hold circuit voltage comparator successive approximation register (sar) controller edge detector edge detector adtrg/intp3/p03 3 a/d conversion result register 0 (adcr0) av ss intad0 intp3 trigger enable analog input channel specification register 0 (ads0) a/d converter mode register 0 (adm0) internal bus note ads02 ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 ads01 ads00 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 adce0 av ref adcs bit selector tap selector 226 chapter 13 a/d converter user s manual u14260ej3v1ud 13.2 a/d converter configuration the a/d converter consists of the following hardware. table 13-1. registers of a/d converter used on software item configuration registers successive approximation register (sar) a/d conversion result register 0 (adcr0) a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) (1) ani0 to ani7 pins these are the analog input pins of the 8-channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin by the analog input channel specification register 0 (ads0) can be used as input port pins. cautions 1. use ani0 to ani7 input voltages within the specification range. if a voltage higher than or equal to av ref or lower than or equal to av ss is applied (even if within the absolute maximum rating range), the conversion value of that or equal to channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani7) pins are alternate-function pins that can also be used as input port pins (p10 to p17). when a/d conversion is performed by selecting any one of ani0 to ani7, do not access port 1 during conversion, as this may cause a lower conversion resolution. 3. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply a pulse to a pin adjacent to the pin in the process of a/d conversion. (2) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started, and holds the sampled analog input voltage value during a/d conversion. (3) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared with the analog input signal. figure 13-2. circuit configuration diagram of series resistor string av ref av ss p-ch series resistor string adcs0 227 chapter 13 a/d converter user? manual u14260ej3v1ud (4) voltage comparator the voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (msb). when the voltage value is converted into a digital value down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transferred to a/d conversion result register 0 (adcr0). (6) a/d conversion result register 0 (adcr0) the result of a/d conversion is loaded from the successive approximation register (sar) to this register each time a/d conversion is completed, and the adcr0 register holds the result of a/d conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) controller after a/d conversion has been completed, intad0 is generated. (8) av ref pin this pin inputs an analog power/reference voltage to the a/d converter. when using the a/d converter, supply the power. connect directly to v ss0 or v ss1 when the a/d converter is not used. the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . caution a series resistor string is connected between the av ref and av ss pins. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (9) av ss pin this is the ground potential pin of the a/d converter. always use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (10) adtrg pin this pin is used to start the a/d converter by hardware. (11) a/d converter mode register 0 (adm0) this register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) analog input channel specification register 0 (ads0) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. 228 chapter 13 a/d converter user s manual u14260ej3v1ud 13.3 registers used in a/d converter the a/d converter uses the following three registers. a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) a/d conversion result register 0 (adcr0) (1) a/d converter mode register 0 (adm0) this register sets the conversion time for the analog input to be a/d converted, conversion start/stop, and the external trigger. adm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears adm0 to 00h. 229 chapter 13 a/d converter user s manual u14260ej3v1ud figure 13-3. format of a/d converter mode register 0 (adm0) address: ff80h after reset: 00h r/w symbol 76543210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 adce0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 f x = 8.38 mhz f x = 12 mhz note 2 0 0 0 144/f x 17.1 s 12.0 s 0 0 1 120/f x 14.3 s 10.0 s note 4 0 1 0 96/f x 11.4 s note 3 8.0 s note 4 1 0 0 72/f x 8.5 s note 3 6.0 s note 4 1 0 1 60/f x 7.1 s note 3 5.0 s note 4 1 1 0 48/f x 5.7 s note 3 4.0 s note 4 other than above setting prohibited ega01 ega00 edge specification of external trigger signal 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection adce0 boost reference voltage generator for a/d converter circuit control note 5 0 stop operation of boost reference voltage generator. 1 enable operation of boost reference voltage generator. notes 1. set the a/d conversion time as follows. when operated at f x = 12 mhz (v dd = 4.5 to 5.5 v): 12 s or more when operated at f x = 8.38 mhz (v dd = 4.0 to 5.5 v): 14 s or more 2. expanded-specification products of pd780078 subseries only. 3. setting is prohibited because the a/d conversion time is less than 14 s. 4. setting is prohibited because the a/d conversion time is less than 12 s. 5. the on-chip booster is provided to realize low-voltage operation. the circuit that generates the reference voltage for boosting is controlled by adce0 and it takes 14 s for operation to stabilize after it is started. therefore, by waiting for at least 14 s to elapse before setting adcs0 to 1 after adce0 has been set to 1, the conversion results are valid from the first result. remark f x : main system clock oscillation frequency 230 chapter 13 a/d converter user s manual u14260ej3v1ud table 13-2. adcs0 and adce0 settings adcs0 adce0 a/d conversion operation 0 0 stop (dc power consumption path does not exist) 0 1 conversion wait mode (only the reference voltage generator consumes power) 1 0 conversion mode (the reference voltage generator stops operation note ) 1 1 conversion mode (the reference voltage generator operates) note the first data immediately after a/d conversion has started must not be used. figure 13-4. timing chart when boost reference voltage generator is used note the time from the rising of the adce0 bit to the rising of the adcs0 bit must be 14 s or longer to stabilize the reference voltage. cautions 1. when rewriting fr00 to fr02 to other than the same data, stop a/d conversion once beforehand. 2. before clearing adce0, clear adcs0. adce0 conversion operation conversion operation conversion wait conversion stop note boost reference voltage adcs0 boost reference voltage generator: operates 231 chapter 13 a/d converter user s manual u14260ej3v1ud (2) analog input channel specification register 0 (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 13-5. format of analog input channel specification register 0 (ads0) address: ff81h after reset: 00h r/w symbol 76543210 ads0 00000 ads02 ads01 ads00 ads02 ads01 ads00 analog input channel specification 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7 caution be sure to clear bits 3 to 7 to 0. (3) a/d conversion result register 0 (adcr0) this is a 16-bit register that stores the a/d conversion results. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register (sar) and held by this register. the most significant bit (msb) is stored in adcr0 first. the higher 8 bits of the conversion results are stored in ff17h. the lower 2 bits of the conversion results are stored in ff16h. adcr0 is read by a 16-bit memory manipulation instruction. reset input sets adcr0 to 0000h. figure 13-6. format of a/d conversion result register 0 (adcr0) caution when a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0) are written, the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0 and ads0. using a timing other than the above may cause an incorrect conversion result to be read. 0 0 0 0 0 0 adcr0 symbol ff17h ff16h address: ff16h, ff17h after reset: 0000h r 232 chapter 13 a/d converter user s manual u14260ej3v1ud 13.4 a/d converter operation 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion using analog input channel specification register 0 (ads0). <2> set bit 0 (adce0) of a/d converter mode register 0 (adm0) to 1 and wait for 14 s or longer. <3> set bit 7 (adcs0) of the adm0 register to 1 to start the a/d conversion operation. (<4> to <10> are operations performed by hardware) <4> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <5> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is finished. <6> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <7> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <8> next, bit 8 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. bit 9 = 1: (3/4) av ref bit 9 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 8 of sar is manipulated as follows. analog input voltage voltage tap: bit 8 = 1 analog input voltage < voltage tap: bit 8 = 0 <9> comparison is continued in this way up to bit 0 of sar. <10> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in a/d conversion result register 0 (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. <11> repeat steps <4> to <10>, until adcs0 is cleared to 0. to stop the a/d converter, clear adcs0 to 0. to restart a/d conversion from the status of adce0 = 1, start from <3>. to restart a/d conversion from the status of adce0 = 0, however, start from <2>. cautions 1. if bit 7 (adcs0) of a/d converter mode register 0 (adm0) is set to 1 without setting bit 0 (adce0) to 1, the first a/d conversion value immediately after a/d conversion has been started may not satisfy the rated value. take measures such as polling the a/d conversion end interrupt request (intad0) and removing the first conversion results. the same may apply if adcs0 is set to 1 without the lapse of a wait time of 14 s (min.) after adce0 has been set to 1. make sure that the specified wait time elapses. 2. the a/d converter stops operation in standby mode. 233 chapter 13 a/d converter user s manual u14260ej3v1ud figure 13-7. basic operation of a/d converter a/d conversion operations are performed continuously until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if a write operation is performed to adm0 or analog input channel specification register 0 (ads0) during an a/d conversion operation, the conversion operation is initialized, and if adcs0 is set (1), conversion starts again from the beginning. reset input sets a/d conversion result register 0 (adcr0) to 0000h. confirm the conversion results by referring to the a/d conversion end interrupt request flag (adif0). conversion time setting adcs0 to 1, external trigger, or overwriting ads0 a/d conversion start delay time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 adcs0 sampling time 200h 300h or 100h 234 chapter 13 a/d converter user s manual u14260ej3v1ud 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the logical a/d conversion result (stored in a/d conversion result register 0 (adcr0)) is shown by the following expression. sar = int ( v ain 1024 + 0.5) av ref adcr0 = sar 64 or (adcr0 0.5) av ref v ain < (adcr0 + 0.5) av ref 1024 1024 where, int( ): function that returns integer part of value in parentheses v ain : analog input voltage av ref :av ref pin voltage adcr0: a/d conversion result register 0 (adcr0) value sar: successive approximation register figure 13-8 shows the relationship between the analog input voltage and the a/d conversion result. figure 13-8. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref sar adcr0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h 235 chapter 13 a/d converter user s manual u14260ej3v1ud 13.4.3 a/d converter operation mode select one analog input channel from among ani0 to ani7 using analog input channel specification register 0 (ads0) to start a/d conversion. a/d conversion can be started in either of the following two ways. hardware start: conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges enabled). software start: conversion is started by setting a/d converter mode register 0 (adm0). when a/d conversion is complete, the interrupt request signal (intad0) is generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 1 after bit 0 (adce0) is set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is input, a/d conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) starts. upon the end of a/d conversion, the conversion result is stored in a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and finished, the a/d conversion operation is not started until a new external trigger signal is input. if adm0 and ads0 are rewritten during a/d conversion, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is restarted from the beginning. if ads0 is rewritten during a/d conversion standby, a/d conversion restarts from the beginning when the following external trigger input signal is input. if 1 is written to adcs0 again during a/d conversion, the a/d conversion in progress is discontinued and the a/d conversion is restarted from the beginning when the next external trigger input signal is input. if 0 is written to adcs0 during a/d conversion, the a/d conversion operation stops immediately. at this time, the conversion result is undefined. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge using bits 1 and 2 (ega00, ega01) of a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1. 236 chapter 13 a/d converter user s manual u14260ej3v1ud figure 13-9. a/d conversion by hardware start (when falling edge is specified) remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 a/d conversion adcr0 adtrg intad0 adm0 set adce0 = 1, adcs0 = 1, trg0 = 1 ads0 rewrite standby state anin anin standby state anin standby state anim anim anim anin anin anin anim anim undefined 237 chapter 13 a/d converter user s manual u14260ej3v1ud (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 0 and 1, respectively, after bit 0 (adce0) is set to 1, a/d conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) starts. upon the end of a/d conversion, the conversion result is stored in a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and finished, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if adm0 and ads0 are rewritten during a/d conversion, the converter suspends a/d conversion and a/d conversion of the selected analog input channel restarts from the beginning. if 1 is written to adcs0 again during a/d conversion, the a/d conversion in progress is discontinued and the a/d conversion is restarted from the beginning. if 0 is written to adcs0 during a/d conversion, the a/d conversion operation stops immediately. at this time, the conversion result is undefined. figure 13-10. a/d conversion by software start remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 adm0 set adce0 = 1, adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim undefined conversion suspended; conversion results are not stored 238 chapter 13 a/d converter user s manual u14260ej3v1ud 13.5 how to read a/d converter characteristics table here, special terms unique to the a/d converters are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per 1 bit of digital output is called 1 lsb (least significant bit). the percentage of 1 lsb with respect to the full scale is expressed by %fsr (full scale range). when the resolution is 10 bits, 1 lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, differential linearity error and errors that are combinations of these express the overall error. note that the quantization error is not included in the overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2 lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2 lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-11. overall error figure 13-12. quantization error ideal line 0 0 1 1 digital output overall error analo g input av ref 0 0 0 1 1 digital output quantization error 1/2 lsb 1/2 lsb analog input av ref 0 239 chapter 13 a/d converter user s manual u14260ej3v1ud (4) zero-scale error this shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0 000 to 0 001. if the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2 lsb) when the digital output changes from 0 001 to 0 010. (5) full-scale error this shows the difference between the actual measured value of the analog input voltage and the theoretical value (full scale 3/2 lsb) when the digital output changes from 1 110 to 1 111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error although the ideal output width for a given code is 1 lsb, this value shows the difference between the actual measured value and the ideal value of the width when outputting a particular code. figure 13-13. zero-scale error figure 13-14. full-scale error figure 13-15. integral linearity error figure 13-16. differential linearity error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref av ref 1 av ref 2 av ref 3 digital output (lower 3 bits) analog input (lsb) ideal line full-scale error 0 av ref digital output analog input integral linearity error ideal line 1 1 0 0 0av ref digital output 1 ...... 1 0 ...... 0 ideal width of 1 lsb differential linearity error analog input 240 chapter 13 a/d converter user s manual u14260ej3v1ud (8) conversion time this expresses the time from when sampling is started to the time when the digital output is obtained. the sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time 241 chapter 13 a/d converter user? manual u14260ej3v1ud 13.6 cautions for a/d converter (1) power consumption in standby mode the a/d converter stops operating in the standby mode. at this time, power consumption can be reduced by setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 (see figure 13-2 ). (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the rated range. in particular, if a voltage of av ref or higher or av ss or lower is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register 0 (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> conflict between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not acknowledged during a/d conversion. therefore, the external trigger signal is not acknowledged during adcr0 write. <3> conflict between adcr0 write and a/d converter mode register 0 (adm0) write or analog input channel specification register 0 (ads0) write adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated. (4) ani0/p10 to ani7/p17 <1> the analog input pins (ani0 to ani7) also function as input port pins (p10 to p17). when a/d conversion is performed with any of pins ani0 to ani7 selected, do not access port 1 while conversion is in progress, as this may reduce the conversion resolution. <2> if digital pulses are applied to the pin adjacent to a pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to the pin adjacent to a pin undergoing a/d conversion. (5) input impedance of ani0 to ani7 pins this a/d converter executes sampling by charging the internal sampling capacitor for approximately 1/8 of the conversion time. therefore, only the leakage current flows during other than sampling, and the current for charging the capacitor flows during sampling. the input impedance therefore varies and has no meaning. to achieve sufficient sampling, it is recommended that the output impedance of the analog input source be 10 k ? or less, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 13-22 ). (6) av ref pin input impedance a series resistor string of several tens of k ? is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. 242 chapter 13 a/d converter user s manual u14260ej3v1ud (7) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if analog input channel specification register 0 (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif0 for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not finished. when a/d conversion is restarted after it is stopped, clear adif0 before restart. figure 13-17. a/d conversion end interrupt request generation timing remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 (8) conversion results just after a/d conversion start if bit 7 (adcs0) of a/d converter mode register 0 (adm0) is set to 1 without setting bit 0 (adce0) to 1, the a/d conversion value immediately after a/d conversion has been started may not satisfy the rated value. take measures such as polling the a/d conversion end interrupt request (intad0) and removing the first conversion results. the same may apply if adcs0 is set to 1 without a lapse of a wait time of 14 s (min.) after adce0 has been set to 1. make sure that the specified wait time elapses. (9) a/d conversion result register 0 (adcr0) read operation when a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0) are written, the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0 and ads0. using a timing other than the above may cause an incorrect conversion result to be read. adm0 rewrite (start of anin conversion) adif is set but anim conversion has not finished. a/d conversion adcr0 adif0 anin anin anim anim anin undefined anim anim ads0 rewrite (start of anim conversion) 243 chapter 13 a/d converter user s manual u14260ej3v1ud (10) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict. therefore, read the a/d conversion result before stopping the a/d operation. figure 13-18 shows the timing of reading the conversion result. figure 13-18. timing of reading conversion result (when conversion result is undefined) (11) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss0 and v ss0 at one location on the board where the voltages are stable. normal conversion result undefined value a/d conversion complete a/d conversion complete normal conversion result is read. a/d conversion is stopped. undefined value is read. adcr0 intad0 adcs0 244 chapter 13 a/d converter user s manual u14260ej3v1ud (12) av ref pin connect a capacitor to the av ref pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and is then started, the voltage applied to the av ref pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref pin. figure 13-19 shows an example of connecting a capacitor. figure 13-19. example of connecting capacitor to av ref pin remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible. av ref v dd0 clamp using a diode with a low v f (0.3 v or lower). av ss c 2 c 1 245 chapter 13 a/d converter user s manual u14260ej3v1ud adcs0 conversion time conversion time a/d conversion start delay time sampling time sampling timing intad0 adcs0 1, external trigger, or ads0 rewrite sampling time (13) a/d converter sampling time and a/d conversion start delay time the sampling time of the a/d converter varies depending on the values set in a/d converter mode register 0 (adm0). there is a delay time from when the a/d converter is enabled for operation until sampling is actually performed. for the sets in which a strict a/d conversion time is required, note the contents described in figure 13-20 and table 13-3. figure 13-20. timing of a/d converter sampling and a/d conversion start delay table 13-3. sampling time and a/d conversion start delay time of a/d converter fr02 fr01 fr00 conversion time note 1 sampling time a/d conversion start delay time min. max. 0 0 0 144/f x 20/f x 0.5/f cpu + 6/f x 0.5/f cpu + 8/f x 0 0 1 120/f x 16/f x 0 1 0 96/f x 12/f x 1 0 0 72/f x 10/f x 0.5/f cpu + 3/f x 0.5/f cpu + 4/f x 1 0 1 60/f x 8/f x 1 1 0 48/f x 6/f x other than above setting prohibited ??? notes 1. set the a/d conversion time as follows. when operated at f x = 12 mhz note 2 (v dd = 4.5 to 5.5 v): 12 s or more when operated at f x = 8.38 mhz (v dd = 4.0 to 5.5 v): 14 s or more 2. expanded-specification products of pd780078 subseries only. remark f x : main system clock oscillation frequency f cpu : cpu clock frequency 246 chapter 13 a/d converter user s manual u14260ej3v1ud (14) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. figure 13-21 shows the internal equivalent circuit of the ani0 to ani7 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to the ani0 to ani7 pins. an example of this is shown in figure 13-22. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. figure 13-21. internal equivalent circuit of pins ani0 to ani7 table 13-4. resistances and capacitances of equivalent circuit (reference values) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? 8 k ? 8 pf 3 pf 2 pf 4.5 v 4 k ? 2.7 k ? 8 pf 1.4 pf 2 pf caution the resistances and capacitances in table 13-4 are not guaranteed values. figure 13-22. example of connection when signal source impedance is high remark n = 0 to 7 c3 c2 r2 r1 c1 anin c3 c2 r2 r1 247 user? manual u14260ej3v1ud chapter 14 serial interface uart0 14.1 functions of serial interface uart0 serial interface uart0 has the following three modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode (fixed to lsb first) this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the communication range is between 1.2 kbps and 131 kbps (when operated at f x = 8.38 mhz). in addition, a baud rate (39 kbps max. (when operated at f x = 1.25 mhz)) can also be defined by dividing the clock input to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). for details, see 14.4.2 asynchronous serial interface (uart) mode . (3) infrared data transfer mode for details, see 14.4.3 infrared data transfer mode . figure 14-1 shows a block diagram of serial interface uart0. 248 chapter 14 serial interface uart0 user? manual u14260ej3v1ud figure 14-1. block diagram of serial interface uart0 note for the configuration of the baud rate generator, refer to figure 14-2 . figure 14-2. block diagram of baud rate generator remark txe0: bit 7 of asynchronous serial interface mode register 0 (asim0) rxe0: bit 6 of asynchronous serial interface mode register 0 (asim0) internal bus receive buffer register 0 (rxb0) rxd0/p23 txd0/p24 pm24 output latch (p24) pe0 fe0 ove0 asynchronous serial interface status register 0 ( asis0) intser0 intst0 baud rate generator note ask0/p25 f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register 0 ( asim0) intsr0 receive controller (parity check) transmit shift register 0 (txs0) transmit controller (parity addition) receive shift register 0 (rx0) tps0 1 tps02 5-bit counter start bit sampling clock tps00 asck0/p25 f x /2 to f x /2 7 selector internal bus 34 mdl0 3 baud rate generator control register 0 (brgc0) mdl0 2 mdl0 1 mdl00 encoder transmit clock txe0 5-bit counter receive clock rxe0 start bit detection 1/2 match match 1/2 249 chapter 14 serial interface uart0 user s manual u14260ej3v1ud 14.2 configuration of serial interface uart0 serial interface uart0 includes the following hardware. table 14-1. configuration of serial interface uart0 item configuration registers transmit shift register 0 (txs0) receive shift register 0 (rx0) receive buffer register 0 (rxb0) control registers asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port register 2 (p2) (1) transmit shift register 0 (txs0) this is a register for setting transmit data. data written to txs0 is transmitted as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transferred as transmit data. writing data to txs0 starts the transmit operation. txs0 can be written by an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs0 to ffh. caution do not write to txs0 during a transmit operation. the same address is assigned to txs0 and receive buffer register 0 (rxb0), so a read operation reads values from rxb0. (2) receive shift register 0 (rx0) this register converts serial data input via the rxd0 pin to parallel data. when one byte of data is received at this register, the receive data is transferred to receive buffer register 0 (rxb0). rx0 cannot be manipulated directly by a program. (3) receive buffer register 0 (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rx0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. in this case, the msb of rxb0 is always 0. rxb0 can be read by an 8-bit memory manipulation instruction. it cannot be written. reset input sets rxb0 to ffh. caution the same address is assigned to rxb0 and transmit shift register 0 (txs0), so during a write operation, values are written to txs0. 250 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (4) transmission controller the transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register 0 (txs0), based on the values set to asynchronous serial interface mode register 0 (asim0). (5) reception controller the reception controller controls receive operations based on the values set to asynchronous serial interface mode register 0 (asim0). during a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register 0 (asis0) according to the type of error that is detected. 14.3 registers to control serial interface uart0 serial interface uart0 uses the following five registers for control functions. asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port register 2 (p2) (1) asynchronous serial interface mode register 0 (asim0) this is an 8-bit register that controls serial interface uart0 s serial transfer operations. asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim0 to 00h. figure 14-3 shows the format of asim0. 251 chapter 14 serial interface uart0 user s manual u14260ej3v1ud figure 14-3. format of asynchronous serial interface mode register 0 (asim0) address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 mode specification note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode operation is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set baud rate generator control register 0 (brgc0) to 10h. caution before writing different data to asim0, stop operation. 252 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (2) asynchronous serial interface status register 0 (asis0) when a receive error occurs in uart mode, this register indicates the type of error. asis0 can be read by an 8-bit memory manipulation instruction. reset input clears asis0 to 00h. figure 14-4. format of asynchronous serial interface status register 0 (asis0) address: ffa1h after reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (parity of transmit data does not match) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register 0 (rxb0)) notes 1. even if the stop bit length is set to two bits by setting bit 2 (sl0) of asynchronous serial interface mode register 0 (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. when an overrun error has occurred, further overrun errors will continue to occur until the contents of receive buffer register 0 (rxb0) are read. (3) baud rate generator control register 0 (brgc0) this register sets the serial clock for the serial interface. brgc0 is set by an 8-bit memory manipulation instruction. reset input clears brgc0 to 00h. figure 14-5 shows the format of brgc0. 253 chapter 14 serial interface uart0 user s manual u14260ej3v1ud figure 14-5. format of baud rate generator control register 0 (brgc0) address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 external clock input to asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 output clock selection for baud rate generator k 0000f sck0 /16 0 0001f sck0 /17 1 0010f sck0 /18 2 0011f sck0 /19 3 0100f sck0 /20 4 0101f sck0 /21 5 0110f sck0 /22 6 0111f sck0 /23 7 1000f sck0 /24 8 1001f sck0 /25 9 1010f sck0 /26 10 1011f sck0 /27 11 1100f sck0 /28 12 1101f sck0 /29 13 1110f sck0 /30 14 1111 setting prohibited cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set brgc0 to 10h when using in infrared data transfer mode. remarks 1. f x : main system clock oscillation frequency 2. f sck0 : source clock for 5-bit counter 3. n: value set via tps00 to tps02 (0 n 7) 4. k: value set via mdl00 to mdl03 (0 k 14) 5. the equation for the baud rate is as follows. [baud rate] = f x [hz] 2 n+1 (k + 16) 254 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (4) port mode register 2 (pm2) port mode register 2 is used to set input/output of port 2 in 1-bit units. to use the p24/txd0 pin as a serial data output, set pm24 and the output latch of p24 to 0. to use the p23/rxd0 pin as a serial data input, and the p25/asck0 pin as a clock input, set pm23 and pm25 to 1. at this time, the output latches of p23 and p25 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 14-6. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) 255 chapter 14 serial interface uart0 user s manual u14260ej3v1ud 14.4 operation of serial interface uart0 this section explains the three modes of serial interface uart0. 14.4.1 operation stop mode because serial transfer is not performed in this mode, the power consumption can be reduced. in addition, pins can be used as ordinary ports. to set the operation stop mode, clear bits 7 and 6 (txe0 and rxe0) of asim0 to 0. (1) register to be used operation stop mode is set by asynchronous serial interface mode register 0 (asim0). asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim0 to 00h. address: ffa0h after reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 14.4.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the communication range is between 1.2 kbps and 131 kbps (when operated at f x = 8.38 mhz). the baud rate (39 kbps max. (when operated at f x = 1.25 mhz)) can be defined by dividing the input clock to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (1) registers to be used asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port register 2 (p2) the basic procedure of setting an operation in the uart mode is as follows. <1> set the brgc0 register (see figure 14-5 ). <2> set bits 5 to 1 (ps01, ps00, cl0, sl0, and isrm0) of the asim0 register and clear bit 0 (irdam0) to 0 (see figure 14-3 ). <3> set bit 7 (txe0) of the asim0 register to 1. transmission is enabled. <4> set bit 6 (rxe0) of the asim0 register to 1. reception is enabled. <5> write data to the txs0 register. data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. 256 chapter 14 serial interface uart0 user s manual u14260ej3v1ud the relationship between the register settings and pins is shown below. table 14-2. relationship between register settings and pins (uart mode) asim0 pm23 p23 pm24 p24 operation mode pin function txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 p23/ p24/ rxd0 txd0 0 1 0/1 0/1 0/1 0/1 0 1 note note reception rxd0 p24 1 0 0/1 0/1 0/1 0/1 0 note note 0 0 transmission p23 txd0 1 1 0/1 0/1 0/1 0/1 0/1 0 1 00 transmission/reception rxd0 txd0 note can be set as port function. remark : don t care, asim0: asynchronous serial interface mode register 0, pm : port mode register, p : port output latch the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. transmit/receive clock generation for baud rate by using main system clock the main system clock is divided to generate the transmit/receive clock. the baud rate generated from the main system clock is determined according to the following formula. [baud rate] = f x [hz] 2 n+1 (k + 16) f x : main system clock oscillation frequency when asck0 is selected as the source clock of the 5-bit counter, substitute the input clock frequency to the asck0 pin for f x in the above expression. n: value set via tps00 to tps02 (0 n 7, see figure 14-5 ) k: value set via mdl00 to mdl03 (0 k 14, see figure 14-5 ) 257 chapter 14 serial interface uart0 user s manual u14260ej3v1ud table 14-3. relationship between main system clock and baud rate error baud rate f x = 8.3886 mhz f x = 8.000 mhz f x = 7.3728 mhz f x = 5.000 mhz f x = 4.1943 mhz (bps) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) 600 7bh 1.14 1200 7bh 1.10 7ah 0.16 78h 0 70h 1.73 6bh 1.14 2400 6bh 1.10 6ah 0.16 68h 0 60h 1.73 5bh 1.14 4800 5bh 1.10 5ah 0.16 58h 0 50h 1.73 4bh 1.14 9600 4bh 1.10 4ah 0.16 48h 0 40h 1.73 3bh 1.14 19200 3bh 1.10 3ah 0.16 38h 0 30h 1.73 2bh 1.14 31250 31h 1.3 30h 0 2dh 1.70 24h 0 21h 1.3 38400 2bh 1.10 2ah 0.16 28h 0 20h 1.73 1bh 1.14 76800 1bh 1.10 1ah 0.16 18h 0 10h 1.73 115200 12h 1.10 11h 2.12 10h 0 remark f x : main system clock oscillation frequency error tolerance range for baud rate the error for the baud rate depends on the number of bits per frame and the 5-bit counter s division ratio [1/(16 + k)]. figure 14-7 shows an example of the baud rate error tolerance range. figure 14-7. error tolerance (when k = 0), including sampling errors baud rate error tolerance (when k = 0) = 15.5 100 = 4.8438 (%) 320 caution the above error tolerance value is the value calculated based on the ideal sample point. in the actual design, allow margins that include errors of timing for detecting a start bit. remark t: 5-bit counter s source clock cycle basic timing start d0 d7 p stop high-speed limit timing start d0 d7 p stop low-speed limit timing start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t 258 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (2) communication operations (a) data format and waveform example figures 14-8 and 14-9 show the format and waveform example of the transmit/receive data. figure 14-8. example of transmit/receive data format in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame character bits 1 data frame consists of the following bits. start bit ............. 1 bit character bits ... 7 bits or 8 bits (lsb first) parity bit ........... even parity, odd parity, zero parity, or no parity stop bit(s) ......... 1 bit or 2 bits asynchronous serial interface mode register 0 (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. when 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. 259 chapter 14 serial interface uart0 user s manual u14260ej3v1ud figure 14-9. example of uart transmit/receive data waveform 1. character bit: 8 bits, parity bit: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. character bit: 7 bits, parity bit: odd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. character bit: 8 bits, parity bit: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop baud rate generator control register 0 (brgc0) is used to set the serial transfer rate. if a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register 0 (asis0). 260 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (b) parity types and operations the parity bit is used to detect bit errors in communication data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of character bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of character bits whose value is 1: the parity bit is 1 if the transmit data contains an even number of character bits whose value is 1: the parity bit is 0 during reception the number of character bits whose value is 1 is counted in the receive data that includes a parity bit, and a parity error occurs when the counted result is an odd number. (ii) odd parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of character bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of character bits whose value is 1: the parity bit is 0 if the transmit data contains an even number of character bits whose value is 1: the parity bit is 1 during reception the number of character bits whose value is 1 is counted in the receive data that includes a parity bit, and a parity error occurs when the counted result is an even number. (iii) zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1 . (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur. 261 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (c) transmission the transmit operation is enabled if bit 7 (txe0) of asynchronous serial interface mode register 0 (asim0) is set to 1, and the transmit operation is started when transmit data is written to transmit shift register 0 (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt request (intst0) is issued. transmission is stopped until the data to be transmitted next is written to txs0. the timing of the transmit completion interrupt request is shown in figure 14-10. intst0 occurs as soon as the last stop bit has been output. figure 14-10. timing of asynchronous serial interface transmit completion interrupt request (i) stop bit length: 1 bit (ii) stop bit length: 2 bits caution do not rewrite asynchronous serial interface mode register 0 (asim0) during a transmit operation. rewriting the asim0 register during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). txd0 (output) d0 d1 d2 d6 d7 parity stop start intst0 txd0 (output) d0 d1 d2 d6 d7 parity start intst0 stop 262 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (d) reception the receive operation performs level detection. the receive operation is enabled when 1 is set to bit 6 (rxe0) of asynchronous serial interface mode register 0 (asim0), and the input via the rxd0 pin is sampled. the serial clock specified by baud rate generator control register 0 (brgc0) is used to sample the rxd0 pin. when the rxd0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxd0 pin input at this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to receive buffer register 0 (rxb0) and intsr0 (receive completion interrupt request) occurs. if the rxe0 bit is reset (to 0) during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 (receive error interrupt request) occur. figure 14-11 shows the timing of the asynchronous serial interface receive completion interrupt request. figure 14-11. timing of asynchronous serial interface receive completion interrupt request caution if the receive operation is enabled with the rxd0 pin input at the low level, the receive operation is immediately started. make sure the rxd0 pin input is at the high level before enabling the receive operation. rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 263 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (e) receive errors three types of errors can occur during a receive operation: a parity error, framing error, or overrun error. if, as the result of data reception, an error flag is set in asynchronous serial interface status register 0 (asis0), a receive error interrupt request (intser0) will occur. receive error interrupts are generated before the receive completion interrupt request (intsr0). table 14-4 lists the causes behind receive errors. as part of receive error interrupt request (intser0) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 14-4 and figure 14-12 ). the contents of asis0 are reset (to 0) when receive buffer register 0 (rxb0) is read or when the next data is received (if the next data contains an error, its error flag will be set). table 14-4. causes of receive errors receive error cause parity error parity specified does not match parity of receive data framing error stop bit was not detected overrun error reception of the next data was completed before data was read from receive buffer register 0 (rxb0) figure 14-12. receive error timing rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 note intser0 (when framing/overrun error occurs) intser0 (when parity error occurs) note even if a receive error occurs when the isrm0 bit has been set (1), intsr0 does not occur. cautions 1. the contents of asynchronous serial interface status register 0 (asis0) are reset (to 0) when receive buffer register 0 (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of receive buffer register 0 (rxb0) after the receive completion interrupt request has occurred even when a receive error has occurred. if rxb0 is not read after the receive completion interrupt request has occurred, overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. 264 chapter 14 serial interface uart0 user s manual u14260ej3v1ud 14.4.3 infrared data transfer mode in infrared data transfer mode, pulses can be output and received in the data format shown in (2). (1) registers to be used asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port register 2 (p2) the relationship between the register settings and pins is shown below. table 14-5. relationship between register settings and pins (infrared data transfer mode) asim0 pm23 p23 pm24 p24 operation mode pin function txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 p23/ p24/ rxd0 txd0 0 1 0/1 0/1 0/1 0/1 0 1 note note reception rxd0 p24 1 0 0/1 0/1 0/1 0/1 0 note note 0 0 transmission p23 txd0 1 1 0/1 0/1 0/1 0/1 0/1 0 1 00 transmission/reception rxd0 txd0 note can be set as port function. caution when using infrared data transfer mode, set baud rate generator control register 0 (brgc0) to 10h. remark : don t care, asim0: asynchronous serial interface mode register 0, pm : port mode register, p : port output latch (2) data format figure 14-13 compares the data format used in uart mode with that used in infrared data transfer mode. the ir (infrared) frame corresponds to the bit string of the uart frame, which consists of pulses that include a start bit, eight data bits, and a stop bit. the length of the electrical pulses that are used to transmit and receive in an ir frame is 3/16 the length of the cycle time for one bit (i.e., the bit time ). this pulse (whose width is 3/16 the length of one bit time) rises from the middle of the bit time (see the figure below). bit time pulse width = 3/16 bit time 265 chapter 14 serial interface uart0 user s manual u14260ej3v1ud figure 14-13. data format comparison between infrared data transfer mode and uart mode (3) relationship between main system clock and baud rate table 14-6 shows the relationship between the main system clock and the baud rate. table 14-6. relationship between main system clock and baud rate f x = 8.3886 mhz f x = 8.000 mhz f x = 7.3728 mhz f x = 5.000 mhz f x = 4.1943 mhz baud rate 131031 bps 125000 bps 115200 bps 78125 bps 65536 bps (4) bit rate and pulse width table 14-7 lists the bit rate, bit rate error tolerance, and pulse width values. table 14-7. bit rate and pulse width values bit rate bit rate error tolerance pulse width minimum value 3/16 pulse width maximum pulse width 266 chapter 14 serial interface uart0 user s manual u14260ej3v1ud (5) input data and internal signals transmit operation timing receive operation timing data reception is delayed for one-half of the specified baud rate. uart output data uart (inverted data) infrared data transfer enable signal txd0 pin output signal start bit stop bit uart transfer data rxd0 input edge detection sampling clock start bit stop bit receive rate conversion data sampling timing 267 chapter 14 serial interface uart0 user s manual u14260ej3v1ud table 14-8. register settings note can be set as port function. caution when using the infrared data transfer mode, set the brgc0 register to 10h. remark : don t care, asim0: asynchronous serial interface mode register 0 brgc0: baud rate generator control register 0, pmxx: port mode register, pxx: output latch of port asim0 txe0 0 rxe0 0 ps01 ps00 cl0 sl0 isrm0 irdam0 tps02 tps01 other than above tps00 mdl03 mdl02 mdl01 mdl00 p23/rxd0 p23 p24/txd0 p24 pm23 note p23 note pm24 note p24 note pin function operation mode stop brgc0 (1) operation stop mode asim0 txe0 0 1 1 rxe0 1 0 1 ps01 0/1 0/1 0/1 ps00 0/1 0/1 0/1 cl0 0/1 0/1 0/1 sl0 0/1 0/1 isrm0 0/1 0/1 irdam0 0 0 0 tps02 0/1 0/1 0/1 tps01 0/1 0/1 0/1 other than above tps00 0/1 0/1 0/1 mdl03 0/1 0/1 0/1 mdl02 0/1 0/1 0/1 mdl01 0/1 0/1 0/1 mdl00 0/1 0/1 0/1 p23/rxd0 rxd0 p23 rxd0 p24/txd0 p24 txd0 txd0 pm23 1 note 1 p23 note pm24 note 0 0 p24 note 0 0 pin function operation mode receive transmit transmit /receive brgc0 (2) asynchronous serial interface (uart) mode setting prohibited asim0 txe0 0 1 1 rxe0 1 0 1 ps01 0/1 0/1 0/1 ps00 0/1 0/1 0/1 cl0 0/1 0/1 0/1 sl0 0/1 0/1 isrm0 0/1 0/1 irdam0 1 1 1 tps02 0 0 0 tps01 0 0 0 other than above tps00 1 1 1 mdl03 0 0 0 mdl02 0 0 0 mdl01 0 0 0 mdl00 0 0 0 p23/rxd0 rxd0 p23 rxd0 p24/txd0 p24 txd0 txd0 pm23 1 note 1 p23 note pm24 note 0 0 p24 note 0 0 pin function operation mode receive transmit transmit /receive brgc0 (3) infrared data transfer mode setting prohibited setting prohibited 268 user? manual u14260ej3v1ud chapter 15 serial interface uart2 serial interface uart2/sio3 can be used in asynchronous serial interface (uart) mode or 3-wire serial i/o mode. caution do not enable uart2 and sio3 at the same time. 15.1 functions of serial interface uart2 serial interface uart2 has the following four modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 15.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode (fixed to lsb first) this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. in addition, a baud rate can also be defined by dividing the clock input to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). for details, see 15.4.2 asynchronous serial interface (uart) mode . (3) multi-processor transfer mode (fixed to lsb first) in this mode data can be transferred to or received from two or more processors. for details, see 15.4.3 multi-processor transfer mode . (4) infrared data transfer (irda) mode (fixed to lsb first) in this mode, pulses can be output or received in the data format of irda specification. this mode can be used to transfer data with another digital device such as a personal computer. for details, see 15.4.4 infrared data transfer (irda) mode . figure 15-1 shows a block diagram of serial interface uart2. chapter 15 serial interface uart2 269 user? manual u14260ej3v1ud figure 15-1. block diagram of serial interface uart2 note for the configuration of the baud rate generator, refer to figure 15-2 . figure 15-2. block diagram of baud rate generator remark txe2: bit 7 of asynchronous serial interface mode register 2 (asim2) rxe2: bit 6 of asynchronous serial interface mode register 2 (asim2) rxb2 rx2 r x d2/so3/p35 t x d2/si3/p34 pe2 fe2 ove2 txs2 intser2 intst2 f x /2 to f x /2 7 txe2 rxe2 ps21 ps20 cl2 sl2 isem2 power2 intsr2 asck2/sck3/p36 txb2 mpr2 internal bus asynchronous serial interface status register 2 (asis2) asynchronous serial interface mode register 2 (asim2) baud rate generator note receive buffer register 2 receive shift register 2 receive controller (parity check) transmit shift register 2 transmit controller (parity addition) transmit buffer register 2 pm34 output latch (pm34) mdl26 mdl27 8-bit counter start bit sampling clock mdl24 asck2/sck3/p36 f x /2 to f x /2 7 selector internal bus 8 mdl23 baud rate generator control register 2 (brgc2) mdl22 mdl21 mdl20 encoder transmit clock txe2 8-bit counter receive clock rxe2 start bit detection 1/2 match match 1/2 mdl25 chapter 15 serial interface uart2 270 user? manual u14260ej3v1ud 15.2 configuration of serial interface uart2 serial interface uart2 includes the following hardware. table 15-1. configuration of serial interface uart2 item configuration registers transmit shift register 2 (txs2) receive shift register 2 (rx2) transmit buffer register 2 (txb2) receive buffer register 2 (rxb2) control registers asynchronous serial interface mode register 2 (asim2) asynchronous serial interface status register 2 (asis2) asynchronous serial interface transmit status register 2 (asif2) baud rate generator control register 2 (brgc2) clock select register 2 (cksel2) transfer mode specification register 2 (trmc2) port mode register 3 (pm3) port register 3 (p3) (1) transmit shift register 2 (txs2) this register transmits the data transferred from transmit buffer register 2 (txb2), as serial data from the txd2 pin. the value of this register is set to ffh if bits 7 and 6 (txe2) of asynchronous serial interface mode register 2 (asim2) are cleared to 0. txs2 cannot be manipulated directly by a program. (2) receive shift register 2 (rx2) this register converts serial data input via the rxd2 pin to parallel data. when one byte of data is received at this register, the receive data is transferred to receive buffer register 2 (rxb2). rx2 cannot be manipulated directly by a program. (3) transmit buffer register 2 (txb2) this register sets data to be transmitted. the data written to txb2 is transferred to transmit shift register 2 (rx2) and transmitted from the txd2 pin as serial data. no data can be written to txb2 if bit 1 (txbf) of transmit status register 2 (asif2) is 1. txb2 is set by an 8-bit memory manipulation instruction. reset input sets txb2 to ffh. (4) receive buffer register 2 (rxb2) this register holds receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rx2). when the data length is set as 7 bits, receive data is transferred to bits 0 to 6 of rxb2. in this case, the msb of rxb2 is always 0. if an overrun error (ove2) occurs, however, the receive data is not transferred to rxb2 but is discarded. rxb2 can be read by an 8-bit memory manipulation instruction. it cannot be written. the value of this register is also initialized to ffh at reset input or by clearing bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) to 0. chapter 15 serial interface uart2 271 user s manual u14260ej3v1ud (5) transmission controller the transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register 2 (txs2), based on the values set to asynchronous serial interface mode register 2 (asim2). (6) reception controller the reception controller controls receive operations based on the values set to asynchronous serial interface mode register 2 (asim2). during a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register 2 (asis2) according to the type of error that is detected. chapter 15 serial interface uart2 272 user s manual u14260ej3v1ud 15.3 registers to control serial interface uart2 serial interface uart2 uses the following eight registers for control functions. asynchronous serial interface mode register 2 (asim2) asynchronous serial interface status register 2 (asis2) asynchronous serial interface transmit status register 2 (asif2) baud rate generator control register 2 (brgc2) clock select register 2 (cksel2) transfer mode specification register 2 (trmc2) port mode register 3 (pm3) port register 3 (p3) (1) asynchronous serial interface mode register 2 (asim2) this is an 8-bit register that controls serial interface uart2 s serial transfer operations. asim2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim2 to 00h. figure 15-3. format of asynchronous serial interface mode register 2 (asim2) (1/2) address: ff90h after reset: 00h r/w symbol 76543210 asim2 power2 txe2 rxe2 ps21 ps20 cl2 sl2 isem2 power2 clock operation enable/stop 0 stop clock operation. power consumption decreases and latch in uart2 is asynchronously reset (t x d2 pin is low). 1 enable clock operation (t x d2 pin is high). note 1 txe2 note 2 transmission enable/stop 0 stop transmission (transmission circuit is synchronously reset). 1 enable transmission. rxe2 note 3 reception enable/stop 0 stop reception (reception circuit is synchronously reset). 1 enable reception. notes 1. in the infrared data transfer (irda) mode, the txd2 pin is at the low level. 2. to transmit data with uart2, first specify the clock operation (set power2 to 1 and then txe2 to 1), wait for the duration of 2 clocks note 4 , and then write the transmit data to transmit buffer register 2 (txb2). to stop transmission by uart2, specify stopping transmission (txe2 = 0), wait for the duration of 2 clocks note 4 , and then stop the clock operation (power2 = 0). 3. to receive data with uart2, first specify the clock operation (set power2 to 1 and then rxe2 to 1), wait for the duration of 2 clocks note 4 , and then start reception. to stop reception by uart2, specify stopping reception (rxe2 = 0), wait for the duration of 2 clocks note 4 , and then stop the clock operation (power2 = 0). 4. the clock is the output clock of the 8-bit counter or the output clock of the baud rate generator. chapter 15 serial interface uart2 273 user s manual u14260ej3v1ud figure 15-3. format of asynchronous serial interface mode register 2 (asim2) (2/2) ps21 note 1 ps20 note 1 parity bit specification transmission reception 0 0 do not output parity bit. reception without parity 0 1 output 0 parity. reception as 0 parity note 2 1 0 output odd parity. identified as odd parity. 1 1 output even parity. identified as even parity. cl2 note 3 data character length specification 0 7 bits 1 8 bits sl2 note 4 specification of number of stop bits for transmission 0 1 bit 1 2 bits isem2 note 5 reception error interrupt signal control 0 intsr2 is generated 1 intser2 is generated notes 1. to specify a parity bit, stop transmission and reception (txe2 = 0 and rxe2 = 0) before rewriting ps21 and ps20. 2. the parity is not identified with this setting. therefore, bit 2 (pe2) of asynchronous serial interface status register 2 (asis2) is not set and the error interrupt does not occur. 3. to specify a data character length, stop transmission and reception (txe2 = 0 and rxe2 = 0) before rewriting cl2. 4. to specify the number of stop bits, stop transmission (txe2 = 0) before rewriting sl2. reception is always performed on the assumption that the number of stop bits is 1. 5. to specify an interrupt that occurs in case of an error, stop reception (rxe2 = 0) before rewriting isem2. chapter 15 serial interface uart2 274 user s manual u14260ej3v1ud (2) asynchronous serial interface status register 2 (asis2) asis2 is a register used to display the error type when a reception error occurs in uart mode. asis2 is read by an 8-bit memory manipulation instruction. reset input clears asis2 to 00h. figure 15-4. format of asynchronous serial interface status register 2 (asis2) address: ff94h after reset: 00h r symbol 76543210 asis2 0000 mpr2 note 1 pe2 note 1 fe2 note 1 ove2 note 1 mpr2 id reception status flag (during reception in multi-processor transfer mode) note 2 0 multi-processor appended bit 1 is not received. 1 multi-processor appended bit 1 is received. pe2 parity error flag 0 no parity error 1 parity error (parity of transmit data does not match note 3 ) fe2 framing error flag 0 no framing error 1 framing error note 4 (stop bit not detected) ove2 overrun error flag 0 no overrun error 1 overrun error note 5 (next receive operation was completed before data was read from receive buffer register 2 (rxb2)) notes 1. these bits are reset to 0 if bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) is reset to 0. 2. this flag is affected only if the multi-processor transfer mode is selected by using bits 6 and 7 (trm02 and trm12) of transfer mode specification register 2 (trmc2). 3. the operation of the parity error flag is affected by the set values of bits 3 and 4 (ps20 and ps21) of asim2. 4. even if the stop bit length is set to two bits by setting bit 2 (sl2) of asim2, stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 5. be sure to read the contents of receive buffer register 2 (rxb2) when an overrun error has occurred. until the contents of rxb2 are read, further overrun errors will occur when receiving data. the next receive data is not written to receive buffer register 2 (rxb2) and is discarded. chapter 15 serial interface uart2 275 user s manual u14260ej3v1ud (3) asynchronous serial interface transmit status register 2 (asif2) this register indicates the status of transmission. asif2 is set by an 8-bit memory manipulation instruction. reset input clears asif2 to 00h. figure 15-5. format of asynchronous serial interface transmit status register 2 (asif2) address: ff95h after reset: 00h r symbol 76543210 asif2 000000 txbf txsf txbf transmit buffer data flag 0 if bit 7 (power2) or bit 6 (txe2) of asynchronous serial interface mode register 2 (asim2) is cleared to 0 if data is transferred to transmit shift register 2 (txs2) 1 if data is written to transmit buffer register 2 (txb2) (if data exists in txb2) txsf transmit shift register data flag 0 if bit 7 (power2) or bit 6 (txe2) of asynchronous serial interface mode register 2 (asim2) is cleared to 0 if no more data is transferred from transmit buffer register 2 (txb2) after completion of transfer. 1 if data is transferred from transmit buffer register 2 (txb2) (during transmission) cautions 1. to start successive transmission, be sure to check that txbf is 0 after the first byte of data has been written to transmit buffer register 2 (txb2), then write the second byte of data to txb2. 2. when successive transmission is in progress, the processing of writing to txb2 can be confirmed by checking the value of txsf after the transmit completion interrupt. ?txsf = 1: successive transmission in progress. one-byte data can be written. ?txsf = 0: successive transmission is complete. two-byte data can be written. when writing, note caution 1 above. 3. to initialize (to set txe2 to 0 or power2 to 0) during successive transmission, make sure that txsf is 0 after the transmit completion interrupt, then initialize. chapter 15 serial interface uart2 276 user s manual u14260ej3v1ud (4) baud rate generator control register 2 (brgc2) this register sets the serial clock for the serial interface. brgc2 is set by an 8-bit memory manipulation instruction. reset input clears brgc2 to 00h. figure 15-6. format of baud rate generator control register 2 (brgc2) address: ff93h after reset: 00h r/w symbol 76543210 brgc2 mdl27 mdl26 mdl25 mdl24 mdl23 mdl22 mdl21 mdl20 output clock mdl27 mdl26 mdl25 mdl24 mdl23 mdl22 mdl21 mdl20 selection for baud k rate generator 00000 setting prohibited 00001000f sck2 /8 8 00001001f sck2 /9 9 00001010f sck2 /10 10 00001011f sck2 /11 11 00001100f sck2 /12 12 00001101f sck2 /13 13 00001110f sck2 /14 14 00001111f sck2 /15 15 00010000f sck2 /16 16 ........ . . ........ . . ........ . . 11111111f sck2 /255 255 caution writing to brgc2 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc2 during a communication operation. before rewriting brgc2, clear bits 5 and 6 (rxe2 and txe2) of asynchronous serial interface mode register 2 (asim2) to 0. remarks 1. f sck2 : source clock for 8-bit counter set by bits 4 to 6 (tps20 to tps22) of clock select register 2 (cksel2) 2. k: value set via mdl27 to mdl20 (8 k 255) 3. n: value set via tps22 to tps20 (0 n 7) 4. the equation for the baud rate is as follows. f x [baud rate] = [hz] 2 n+1 k chapter 15 serial interface uart2 277 user s manual u14260ej3v1ud (5) clock select register 2 (cksel2) this 8-bit register is used to select the input clock for the baud rate of uart2 and the transmit pulse width of irda. cksel2 is set by an 8-bit memory manipulation instruction. reset input clears cksel2 to 00h. figure 15-7. format of clock select register 2 (cksel2) address: ff92h after reset: 00h r/w symbol 76543210 cksel2 0 tps22 note tps21 note tps20 note tpw23 tpw22 tpw21 tpw20 tps22 tps21 tps20 source clock of 8-bit counter n 0 0 0 external clock input to asck2 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 tpw23 tpw22 tpw21 tpw20 selection of irda transmit pulse width of 1-bit data 0010 width of two f sck2 clocks 0011 width of three f sck2 clocks 0100 width of four f sck2 clocks 0101 width of five f sck2 clocks 0110 width of six f sck2 clocks 0111 width of seven f sck2 clocks 1000 width of eight f sck2 clocks 1001 width of nine f sck2 clocks 1010 width of ten f sck2 clocks 1011 width of 11 f sck2 clocks 1100 width of 12 f sck2 clocks 1101 width of 13 f sck2 clocks 1110 width of 14 f sck2 clocks 1111 width of 15 f sck2 clocks 0000 width of 16 f sck2 clocks other than above setting prohibited note to rewrite tps20 to tps22, clear bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) to 0. chapter 15 serial interface uart2 278 user s manual u14260ej3v1ud cautions 1. if data is written to cksel2 during a communication operation, the output of the baud rate generator is disturbed and the communication cannot be performed correctly. therefore, do not rewrite cksel2 during communication. 2. to transfer data in the infrared data transfer (irda) mode, the following conditions must be satisfied when the transmit pulse width is specified. (condition) 1.41 s transmit pulse width < transfer rate set values of bits 0 to 3 set values of bits 0 to 7 (tpw20 to tpw23) of cksel2 (mdl20 to mdl27) of brgc2 example if the transmit pulse width is set to the width of three f sck2 clocks (tpw23 to tpw20 = 0, 0, 1, 1) remark f x : main system clock oscillation frequency f sck2 : source clock of 8-bit counter t x d2 pin input clock 1-bit cycle 3-clock width pulse output starts from the center of the 1-bit cycle. chapter 15 serial interface uart2 279 user s manual u14260ej3v1ud (6) transfer mode specification register 2 (trmc2) this 8-bit register is used to specify the transfer mode, switch the interrupt source of intst2, enable or disable occurrence of the receive completion interrupt in the multi-processor transfer mode, and specify the multi- processor transfer appended bit. trmc2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets trmc2 to 02h. figure 15-8. format of transfer mode specification register 2 (trmc2) address: ff91h after reset: 02h r/w symbol 76543210 trmc2 trm12 note 1 trm02 note 1 0 0 ismd2 0 mpien2 mps2 note 2 trm12 trm02 transfer mode 0 0 uart transfer mode note 3 0 1 multi-processor transfer mode note 3 1 0 infrared data transfer (irda) mode note 3 11 mpien2 receive completion interrupt enable/disable in multi-processor transfer mode note 4 condition intsr2 enable/disable note 5 0 notes 6, 7 if 0 is written to this bit disabled 1 if bit 7 (power2) or bit 6 (txe2) of enabled asynchronous serial interface mode register 2 (asim2) is cleared to 0 if bit data has been received with multi- processor appended bit of 1 ismd2 note 8 switching interrupt source of intst2 0 intst2 occurs when transmission completed 1 intst2 occurs when data transfer completed mps2 setting of multi-processor transmission appended bit note 4 0 appends 0 as and transmits multi-processor appended bit (during data transmission). 1 appends 1 as and transmits multi-processor appended bit (during id transmission). notes 1. before rewriting trm12 and trm02, clear bits 6 (txe2) and 5 (rxe2) of asynchronous serial interface mode register 2 (asim2) to 0. 2. before setting a value to mps2, confirm that bit 1 (txbf) of asynchronous serial interface transmit status register 2 (asif2) is cleared to 0. before writing transmit data to transmit buffer register 2 (txb2), specify whether 0 or 1 is appended as the multi-processor appended bit. 3. the setting of bits 0 to 4 (isem2, sl2, cl2, ps20, and ps21) of asim2 is valid in all the transfer modes. 4. the specification by mpien2 and mps2 is valid only when bit 7 (trm12) is cleared to 0 and bit 6 (trm02) is set to 1 (i.e., when the multi-processor transfer mode is set). chapter 15 serial interface uart2 280 user s manual u14260ej3v1ud notes 5. enabling or disabling the occurrence of the receive completion interrupt (intsr2) in the case of an error is affected by the setting of bit 0 (isem2) of asim2. 6. even if mpien is cleared to 0, reception is started when the start bit is detected, in order to detect address (id) reception. at this time, an error in the receive data is not detected if the multi-processor appended bit is 0 . if data 1 is received by mistake, due to bit slip or other cause, when the multi- processor appended bit is detected, however, id reception is detected. consequently, the error in the receive data is identified, and the error interrupt signal may be generated and the error flag set. 7. when bit 7 (power2) and bit 5 (rxe2) of asim2 have not been set to 1, mpien2 cannot be cleared to 0 (remain 1) even if 0 is written to it. 8. before setting ismd2, clear bit 6 (txe2) of asynchronous serial interface mode register 2 (asim2) to 0. remark when receiving data in the multi-processor transfer mode, the receive completion interrupt (intsr2) occurs, regardless of the value of mpien2, if data with the multi-processor appended bit set to 1 is received. usually, this receive data is an address (id) that indicates the other party of communication. the subsequent receive data can be ignored and the occurrence of an unnecessary receive completion interrupt (intsr2) can be disabled by comparing this received id with the id of the microcontroller (for which software processing is necessary) and clearing mpien2 if the two ids do not match. (7) port mode register 3 (pm3) pm3 is a register that sets the input/output of port 3 in 1-bit units. to use the p34/txd2/si3 pin as a serial data output, set pm34 and the output latch of p34 to 0. to use the p35/rxd2/so3 pin as a serial data input, and the p36/asck2/sck3 pin as a clock input, set pm35 and pm36 to 1. at this time, the output latches of p35 and p36 can be either 0 or 1. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 15-9. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n i/o mode selection of p3n pin (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 15 serial interface uart2 281 user s manual u14260ej3v1ud 15.4 operation of serial interface uart2 this section explains the four modes of serial interface uart2. 15.4.1 operation stop mode because serial transfer is not performed in this mode, the power consumption can be reduced. in addition, pins can be used as ordinary ports. to set the operation stop mode, clear bits 7, 6, and 5 (power2, txe2, and rxe2) of asim2 to 0. (1) register to be used operation stop mode is set by asynchronous serial interface mode register 2 (asim2). asim2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim2 to 00h. address: ff90h after reset: 00h r/w symbol 76543210 asim2 power2 txe2 rxe2 ps21 ps20 cl2 sl2 isem2 power2 clock operation enable/stop 0 stop clock operation. power consumption decreases and latch in uart2 is asynchronously reset (t x d2 pin is low). txe2 note 1 transmission enable/stop 0 stop transmission (transmission circuit is synchronously reset). rxe2 note 1 reception enable/stop 0 stop reception (reception circuit is synchronously reset). notes 1. to stop serial transmission/reception, wait for the duration of 2 clocks note 2 after specifying stopping the transmission/reception (txe2 = 0 or rxe2 = 0), and then stop the clock operation (power2 = 0). 2. the clock is the output clock of the 8-bit counter or the output clock of the baud rate generator. chapter 15 serial interface uart2 282 user s manual u14260ej3v1ud 15.4.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (1) registers to be used asynchronous serial interface mode register 2 (asim2) asynchronous serial interface status register 2 (asis2) baud rate generator control register 2 (brgc2) asynchronous serial interface transmit status register 2 (asif2) clock select register 2 (cksel2) transfer mode specification register 2 (trmc2) port mode register 3 (pm3) port register 3 (p3) the basic procedure of setting an operation in the uart mode is as follows. <1> set the cksel2 register (see figure 15-7 ). <2> set the brgc2 register (see figure 15-6 ). <3> clear bits 7 and 6 (trm12 and trm02) of the trmc2 register to 0 and set bit 3 (ismd2) (see figure 15-8 ). <4> set bits 4 to 0 (ps21, ps20, cl2, sl2, and isem2) of the asim2 register (see figure 15-3 ). <5> set bit 7 (power2) of the asim2 register to 1. <6> set bit 6 (txe2) of the asim2 register to 1. transmission is enabled. <7> set bit 5 (rxe2) of the asim2 register to 1. reception is enabled. <8> write data to txb2. data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins (uart mode) asim2 trmc2 pm34 p34 pm35 p35 operation pin function pow txe2 rxe2 ps21 ps20 cl2 sl2 i sem2 trm12 trm02 ismd2 mpien2 mps2 mode p34/ p35/ er2 si3/ so3/ txd2 rxd2 1 0 1 0/1 0/1 0/1 0/1 0 0 note note 1 reception p34 rxd2 1 1 0 0/1 0/1 0/1 0/1 0 0 0/1 00 note note transmission txd2 p35 1 1 1 0/1 0/1 0/1 0/1 0/1 0 0 0/1 001 transmission/ txd2 rxd2 reception note can be set as port function. caution when using uart2, stop the operation of sio3 (bit 7 (csie3) of serial operation mode register 3 (csim3) = 0). remark : don t care, asim2: asynchronous serial interface mode register 2, trmc2: transfer mode specification register 2, pm : port mode register, p : port output latch chapter 15 serial interface uart2 283 user s manual u14260ej3v1ud the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. transmit/receive clock generation for baud rate by using main system clock the main system clock is divided to generate the transmit/receive clock. the baud rate generated from the main system clock is determined according to the following formula. [baud rate] = f x [hz] 2 n+1 k f x : main system clock oscillation frequency when asck2 is selected as the source clock of the 8-bit counter, substitute the input clock frequency to asck2 pin for f x in the above expression. n: value set via tps20 to tps22 (0 n 7, see figure 15-7 ) k: value set via mdl27 to mdl20 (8 k 255, see figure 15-6 ) baud rate error the baud rate error can be calculated by the following expression. [baud rate error] = baud rate [bps] 100 100 [%] targeted baud rate [bps] table 15-3 shows an example of the relationship between the main system clock and a baud rate. table 15-3. relationship between main system clock and baud rate baud rate [bps] f x = 7.37 mhz f x = 5.0 mhz f x = 4.19 mhz n k error (%) n k error (%) n k error (%) 300 7 96 0.04 7 65 0.16 6 109 0.11 600 7 48 0.04 6 65 0.16 5 109 0.11 1200 7 24 0.04 5 65 0.16 4 109 0.11 2400 6 24 0.04 4 65 0.16 3 109 0.11 4800 5 24 0.04 3 65 0.16 2 109 0.11 9600 4 24 0.04 2 65 0.16 1 109 0.11 19200 3 24 0.04 1 65 0.16 31250 1 59 0.07 1 40 0 38400 2 24 0.04 76800 1 24 0.04 remark f x : main system clock oscillation frequency n: value set by tps20 to tps22 (0 n 7) k: value set by mdl27 to mdl20 (8 k 255) chapter 15 serial interface uart2 284 user s manual u14260ej3v1ud permissible baud rate range for reception figure 15-10. minimum permissible data frame length and maximum permissible data frame length as shown in the timing chart in figure 15-10, the latch timing of the receive data is determined by the counter set by using baud rate generator control register 2 (brgc2) after the start bit has been detected. if the last data (stop bit) is received within this latch timing, the data can be correctly received. this latch timing has a margin of two clocks. take reception of 11-bit data as an example. 1 bit data length of uart2: fl = (brate) 1 minimum permissible data frame length: flmin = 11 fl k 2 fl 2k = 21k + 2 fl 2k therefore, the maximum receivable baud rate of the transmission destination is as follows. brmax = (flmin/11) 1 = 22k brate 21k + 2 start d0 fl d1 stop d7 p start d0 d1 stop d7 p flmin start d0 d1 stop d7 p flmax data frame length of uart2 minimum permissible data frame length maximum permissible data frame length 1 data frame (11 fl) chapter 15 serial interface uart2 285 user s manual u14260ej3v1ud similarly, the maximum permissible data frame length is as follows. 10 flmax = 11 fl k + 2 fl 11 2k = 21k 2 fl 2k flmax = 21k 2 fl 11 20k therefore, the minimum receivable baud rate of the transmission destination is as follows. brmin = (flmax/11) 1 = 20k brate 21k 2 remark brate: baud rate of uart2 k: value set by mdl27 to mdl20 (8 k 255) fl: 1 bit data length from the above expressions for the maximum and minimum baud rates, the permissible error of the baud rate between uart2 and the transmission destination can be calculated as follows. table 15-4. maximum permissible baud rate error and minimum permissible baud rate error k maximum permissible baud rate error (%) minimum permissible baud rate error (%) 8 +3.53 3.61 20 +4.26 4.31 50 +4.56 4.58 100 +4.66 4.67 255 +4.72 4.73 caution the above error tolerance value is the value calculated based on the ideal sample point. in the actual design, allow margins that include errors of timing for detecting a start bit. remark k: value set by mdl27 to mdl20 (8 k 255) the accuracy of reception is dependent upon the number of bits in one frame, input clock frequency, and division ratio k (the higher the input clock frequency and the higher the division ratio k, the higher the accuracy). chapter 15 serial interface uart2 286 user s manual u14260ej3v1ud (2) communication operations (a) data format and waveform example figures 15-11 and 15-12 show the format and waveform example of the transmit/receive data. figure 15-11. example of transmit/receive data format in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame character bits 1 data frame consists of the following bits. start bit ............. 1 bit character bits ... 7 bits or 8 bits (lsb first) parity bit ........... even parity, odd parity, zero parity, or no parity stop bit(s) ......... 1 bit or 2 bits asynchronous serial interface mode register 2 (asim2) is used to set the character bit length, parity selection, and stop bit length within each data frame. when 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. chapter 15 serial interface uart2 287 user s manual u14260ej3v1ud figure 15-12. example of uart transmit/receive data waveform 1. character bit: 8 bits, parity bit: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. character bit: 7 bits, parity bit: odd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. character bit: 8 bits, parity bit: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop baud rate generator control register 2 (brgc2) and clock select register 2 (cksel2) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register 2 (asis2). chapter 15 serial interface uart2 288 user s manual u14260ej3v1ud (b) parity types and operations the parity bit is used to detect bit errors in communication data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity during transmission the number of character bits in transmit data that includes a parity bit is controlled so that there are an even number of bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of character bits whose value is 1: the parity bit is 1 if the transmit data contains an even number of character bits whose value is 1: the parity bit is 0 during reception the number of character bits whose value is 1 is counted in the receive data that includes a parity bit, and a parity error occurs when the counted result is an odd number. (ii) odd parity during transmission the number of character bits in transmit data that includes a parity bit is controlled so that there is an odd number of bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of character bits whose value is 1: the parity bit is 0 if the transmit data contains an even number of character bits whose value is 1: the parity bit is 1 during reception the number of character bits whose value is 1 is counted in the receive data that includes a parity bit, and a parity error occurs when the counted result is an even number. (iii) zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1 . (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur. chapter 15 serial interface uart2 289 user s manual u14260ej3v1ud (c) transmission if the uart transfer mode is selected by using transfer mode specification register 2 (trmc2) and bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) is set to 1, the t x d2 pin outputs a high level. if bit 6 (txe2) of asim2 is set to 1 next, transmission is enabled. transmission can be started by writing transmit data to transmit buffer register 2 (txb2). the start bit, parity bit, and stop bit are automatically appended to the transmit data. when transmission has been started, the data in txb2 is transferred to transmit shift register 2 (txs2) and is sequentially output to the t x d2 pin, starting from the lsb. if the data to be transmitted next has been written to txb2 by the time transmission is complete, transmitting the next data is started. if no more data has been written to txb2, transmission is stopped until the next data is written. figure 15-13 illustrates the timing of the transmit interrupt. figure 15-13. timing of asynchronous serial interface transmit completion interrupt request (i) stop bit length: 1 bit, trmc2: ismd2 = 0 txd2 (output) d0 d1 d2 d6 d7 parity stop start intst2 (ii) stop bit length: 2 bits, trmc2: ismd2 = 0 t x d2 (output) intst2 d0 start d1 d2 d6 d7 parity stop (iii) successive transmission, stop bit length: 2 bits, trmc2: ismd2 = 1 intst2 d0 d0 start if next transmit data is written to txb2 start d1 d7 parity stop txd2 (output) remark trmc2: transfer mode specification register 2 ismd2: bit 3 of trmc2 chapter 15 serial interface uart2 290 user s manual u14260ej3v1ud caution do not rewrite asynchronous serial interface mode register 2 (asim2) during a transmit operation. rewriting the asim2 register during a transmit operation may disable further transmit operations (in such cases, input a reset to restore normal operation). (d) successive transmission the next transmit data can be written to transmit buffer register 2 (txb2) as soon as transmit shift register 2 (txb2) has started its shift operation. consequently, even while an interrupt is being serviced after one data frame has been transmitted, data can be successively transmitted. to successively transmit data, be sure to check, by using asynchronous serial interface transmit status register 2 (asif2), the transmission status and whether writing to txb2 is enabled or disabled, and then write the data to txb2. the following table shows the relationship between the transmission status and writing to txb2. table 15-5. writing to txbf and txb2 (when successive transmission is started) txbf writing to txb2 when successive transmission is started 0 enabled 1 disabled caution when starting successive transmission, write the first byte of data to transmit buffer register 2 (txb2), and then make sure to write data to txb2 again. remark txbf: bit 1 of asif2 table 15-6. writing to txsf and txb2 (when successive transmission is in progress) txsf writing to txb2 when successive transmission is in progress 0 two-byte writing or transmit completion processing enabled 1 one-byte writing enabled cautions 1. when successive transmission is in progress, the processing of writing to txb2 can be confirmed by checking the value of txsf after the transmit completion interrupt. ?txsf = 1: successive transmission in progress. one-byte data can be written. ?txsf = 0: successive transmission is complete. two-byte data can be written. when writing, note the caution in table 15-5. 2. to initialize (to set txe2 to 0 or power2 to 0) during successive transmission, make sure that txsf is 0 after the transmit completion interrupt, then initialize. chapter 15 serial interface uart2 291 user s manual u14260ej3v1ud figure 15-14 shows the processing flow of successive transmission. figure 15-14. processing flow of successive transmission start set various registers write data to txb2 read asif2 interrupt occurred read asif2 txsf = 0? txsf = 1? read asif2 completion of transmission processing write data to txb2 wait for occurrence of interrupt required number of writes performed? txbf = 0? no no no no yes yes yes yes chapter 15 serial interface uart2 292 user s manual u14260ej3v1ud the following figures and tables show the timing of starting and completing successive transmission. figure 15-15. timing of starting successive transmission start stop start parity data (1) ff data (2) data (3) data (1) ff <2> <3> <4> <5> data (1) data transfer data transfer intst2 txb2 txs2 txbf txsf data transfer data (2) t x d2 (output) data (1) start parity stop data (3) <1> table 15-7. timing of starting successive transmission transmission procedure internal operation txbf txsf set transmission mode. <1> starts transmission unit. 0 0 write data (1). 10 <2> generates start bit and starts 0 1 transmitting data (1). read asif2 (to confirm txbf = 0) 1 1 and write data (2). (during transmission) <3> interrupt (intst2) occurs. 0 1 read asif2 (to confirm txbf = 0) 1 1 and write data (3). <4> generates start bit and starts transmitting data (2). (during transmission) <5> interrupt (intst2) occurs. 0 1 read asif2 (to confirm txbf = 0) 1 1 and write data (3). remarks 1. <1> to <5> in this table correspond to <1> to <5> in figure 15-15. 2. txbf: bit 1 (transmit buffer data flag) of asynchronous serial interface transmit status register 2 (asif2) txsf: bit 0 of asif2 (transmit shift register data flag) chapter 15 serial interface uart2 293 user s manual u14260ej3v1ud figure 15-16. timing of completing successive transmission ff intst2 txb2 txs2 txsf txbf ff t x d2 (output) parity parity parity stop stop stop start start data (n ? 1) data (n ? 1) <1> <2> <4> <3> <5> <6> data (n ? 1) data (n) data (n ? 1) data (n) power2 or txe2 is cleared. data transfer data transfer table 15-8. timing of completing successive transmission transmission procedure internal operation txbf txsf <1> data (n 2) is transmitted. 1 1 <2> interrupt (intst2) occurs. 0 1 read asif2 (to confirm txbf = 0) 1 1 and write data (n). <3> generates start bit and starts transmitting data (n 1). (during transmission) <4> interrupt (intst2) occurs. 0 1 read asif2 (to confirm txbf = 0). 1 1 no data to be written. <5> generates start bit and starts transmitting data (n). (during transmission) <6> interrupt (intst2) occurs. 0 0 read asif2 (to confirm txbf = 0) initializes internal circuit. and clear power2 or txe2. remarks 1. <1> to <6> in this table correspond to <1> to <6> in figure 15-16. 2. txbf: bit 1 (transmit buffer data flag) of asynchronous serial interface transmission status register 2 (asif2) txsf: bit 0 of asif2 (transmit shift register data flag) power2: bit 7 of asynchronous serial interface mode register 2 (asim2) txe2: bit 6 of asim2 chapter 15 serial interface uart2 294 user s manual u14260ej3v1ud (d) reception the interface enters the reception wait status if the uart transfer mode is specified by using transfer mode specification register 2 (trmc2) and bit 5 (rxe2) of asynchronous serial interface mode register 2 (asim2) is set to 1 after bit 7 (power2) has been set to 1. in this status, the r x d2 pin is monitored to detect the start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 2 (rx2) at the specified baud rate. when the stop bit is received, a receive completion interrupt (intsr2) occurs and, at the same time, the data in rx2 is written to receive buffer register 2 (rxb2). if an overrun error (ove2) occurs, however, the receive data is not written to rxb2 but discarded. even if a parity error (pe2) or framing error (fe2) occurs during reception, reception continues up to the position at which the stop bit is received, and an error interrupt (intsr2/intser2) occurs after completion of reception. figure 15-17. timing of asynchronous serial interface receive completion interrupt request rxd2 (input) d0 d1 d2 d6 d7 parity stop start intsr2 rxb2 caution during reception, the number of stop bits is always 1. a second stop bit is ignored. chapter 15 serial interface uart2 295 user s manual u14260ej3v1ud (e) receive errors three types of errors can occur during a receive operation: a parity error, framing error, or overrun error. if, as the result of data reception, an error flag is set in asynchronous serial interface status register 2 (asis2), a receive error interrupt request (intsr2/intser2) will occur. table 15-9 lists the causes behind receive errors. as part of receive error interrupt request (intsr2/intser2) servicing, the contents of asis2 can be read to determine which type of error occurred during the receive operation (see table 15-9 and figure 15-18 ). the contents of asis2 are reset (to 0) when receive buffer register 2 (rxb2) is read or when the next data is received (if the next data contains an error, its error flag will be set). table 15-9. causes of receive errors receive error cause parity error specified parity does not match parity of receive data framing error stop bit was not detected overrun error reception of the next data was completed before data was read from receive buffer register 2 (rxb2) caution even if data is written to txb2 when data remains in transmit buffer register 2 (txb2), an overrun error will not occur. figure 15-18. receive error timing cautions 1. the contents of asynchronous serial interface status register 2 (asis2) are reset (to 0) when receive buffer register 2 (rxb2) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis2 before reading rxb2. 2. be sure to read the contents of receive buffer register 2 (rxb2) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb2 are read. note the interrupts can be divided into intsr2 and intser2 by setting bit 0 (isem2) of asynchronous serial interface mode register 2 (asim2) to 1. rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr2 or intser2 note chapter 15 serial interface uart2 296 user s manual u14260ej3v1ud figure 15-19. intsr2 and intser2 (1) if isem2 is cleared to 0 (error interrupt is included in intsr2) (a) no error at reception (b) error at reception intsr2 intser2 intsr2 intser2 (2) if isem2 is set to 1 (to separate intsr2 and intser2) (a) no error at reception (b) error at reception intsr2 intser2 intsr2 intser2 chapter 15 serial interface uart2 297 user s manual u14260ej3v1ud 15.4.3 multi-processor transfer mode in this mode, data can be transferred to or received from two or more processors. (1) registers to be used asynchronous serial interface mode register 2 (asim2) asynchronous serial interface status register 2 (asis2) baud rate generator control register 2 (brgc2) asynchronous serial interface transmit status register 2 (asif2) clock select register 2 (cksel2) transfer mode specification register 2 (trmc2) port mode register 3 (pm3) port register 3 (p3) the basic procedure of setting an operation in the multi-processor transfer mode is as follows. <1> set the cksel2 register (see figure 15-7 ). <2> set the brgc2 register (see figure 15-6 ). <3> set bits 7 and 6 (trm12 and trm02) of the trmc2 register to 0 and 1, and set bits 3, 1, and 0 (ismd2, mpien2, and mps2) (see figure 15-8 ). <4> set bits 4 to 0 (ps21, ps20, cl2, sl2, and isem2) of the asim2 register (see figure 15-3 ). <5> set bit 7 (power2) of the asim2 register to 1. <6> set bit 6 (txe2) of the asim2 register to 1. transmission is enabled. <7> set bit 5 (rxe2) of the asim2 register to 1. reception is enabled. <8> write data to txb2. data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 15-10. relationship between register settings and pins (multi-processor transfer mode) asim2 trmc2 pm34 p34 pm35 p35 operation pin function pow txe2 rxe2 ps21 ps20 cl2 sl2 i sem2 trm12 trm02 ismd2 mpien2 mps2 mode p34/ p35/ er2 si3/ so3/ txd2 rxd2 1 0 1 0/1 0/1 0/1 0/1 0 1 0/1 0/1 note note 1 reception p34 rxd2 1 1 0 0/1 0/1 0/1 0/1 0 1 0/1 0/1 0/1 0 0 note note transmission txd2 p35 1 1 1 0/1 0/1 0/1 0/1 0/1 0 1 0/1 0/1 0/1 0 0 1 transmission/ txd2 rxd2 reception note can be set as port function. caution when using uart2, stop the operation of sio3 (bit 7 (csie3) of serial operation mode register 3 (csim3) = 0). remark : don t care, asim2: asynchronous serial interface mode register 2, trmc2: transfer mode specification register 2, pm : port mode register, p : port output latch chapter 15 serial interface uart2 298 user s manual u14260ej3v1ud for an explanation how to generate the transmit/receive clock for the baud rate and details of the permissible error range of the baud rate, refer to (1) registers to be used in 15.4.2 asynchronous serial interface (uart) mode . (2) communication operations (a) data format figure 15-20 shows an example of the transmit/receive data format. figure 15-20. example of transmit/receive data format in multi-processor transfer mode (1) id transfer (multi-processor appended bit = 1) format character bit: 8 bits, no parity, stop bit: 1 bit, communication data: 55h d0 start bit stop bit d1 d2 d3 d4 d5 d6 d7 appended bit 1 data frame character bit (2) data transfer (multi-processor appended bit = 0) format character bit: 8 bits, parity bit: odd parity, stop bit: 1 bit, communication data: 55h d0 d1 d2 d3 d4 d5 d6 d7 start bit stop bit parity bit appended bit 1 data frame character bit caution if parity is specified, the parity bit is output after the multi-processor appended bit. in this case, the multi-processor appended bit is subject to parity calculation during both transmission and reception. chapter 15 serial interface uart2 299 user s manual u14260ej3v1ud one data frame consists of the following bits: start bit ........................................... 1 bit character bit ................................... 7/8 bits (lsb first) multi-processor appended bit ........ 1 bit (set to 1 or 0) parity bit .......................................... even/odd/0/none stop bit ........................................... 1/2 bits the character bit length, parity, and stop bit length in one data frame are selected by asynchronous interface mode register 2 (asim2). data is transferred starting from the lsb. the multi-processor appended bit of transmit data is specified by transfer mode specification register 2 (trmc2). the serial transfer rate is selected by baud rate generator control register 2 (brgc2) and clock select register 2 (cksel2). if an error occurs when receiving serial data, the error can be determined by reading the status of asynchronous serial interface status register 2 (asis2). chapter 15 serial interface uart2 300 user s manual u14260ej3v1ud (b) transmission if the multi-processor transfer mode is set by using transfer mode specification register 2 (trmc2) and bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) is set to 1, the txd2 pin outputs a high level. if bit 6 (txe2) of asim2 is set to 1 next, transmission is enabled. transmission (id transmission) can be started by setting bit 0 (mps2) of trmc2 to 1 and writing transmit data to transmit buffer register 2 (txb2). next, confirm that bit 1 (txbf) of asynchronous serial interface transmit status register 2 (asif2) is 0. then clear mps and write transmit data to txb2 (data transmission). the start bit, multi-processor transfer appended bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb2 is transferred to transmit shift register 2 (txs2) and sequentially output to the txd2 pin, starting from the lsb. if the data to be transmitted next has been written to txb2 by the time transmission is complete, transmitting the next data is started. if no more data has been written to txb2, transmission is stopped until new transmit data is written. figure 15-21 shows the timing of a transmit interrupt. figure 15-21. timing of transmit completion interrupt request in multi-processor transfer mode d0 start start d7 mps2 stop start mps2 stop d0 d7 ff data 1 (id) data 2 (data) data 3 (data) ff txd2 (output) intst2 txb2 txs2 cpu mps2 mps2 1 mps2 0 txb2 data 1 (id) txb2 data 2 (data) txb2 data 3 (data) id transmit frame data transmit frame data 1 (id data) data 2 (data) data transfer data transfer caution before writing transmit data to txb2, confirm that txbf = 0 and set or clear the mps bit. if the mps bit is set or cleared with txbf = 1, the set data of the mps bit may be appended to the transmit data currently in txb2 and transferred. chapter 15 serial interface uart2 301 user s manual u14260ej3v1ud (c) reception the interface enters the reception wait status if the multi-processor transfer mode is specified by using transfer mode specification register 2 (trmc2) and bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) is set to 1 and then bit 5 (rxe2) is set to 1. in this status, the r x d2 pin is monitored to detect the start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 2 (rx2) at the specified baud rate. if data with the multi-processor appended bit set to 1 is received (id reception), a receive completion interrupt (intsr2) occurs after the stop bit has been detected and, at the same time, the data in rx2 is written to receive buffer register 2 (rxb2). at this time, bit 3 (mpr2) of asynchronous serial interface register 2 (asis2) is set to 1. after it has been confirmed that mpr2 is 1, the id of the receive data and the id of the microprocessor are compared (for which software processing is necessary). if the two ids match, the interface prepares for the next reception and waits for the next receive completion interrupt (intsr2). if the ids do not match, clear bit 1 (mpien2) of transfer mode specification register 2 (trmc2) to 0. this makes receive data other than id invalid and prevents occurrence of an unwanted receive completion interrupt (intsr2). figure 15-22. timing of receive completion interrupt request in multi-processor transfer mode (1/2) (1) if receive data matches id d0 start start stop start stop d7 mpr2 mpr2 d0 d7 d0 ff data 1 (id) data 2 (data) rxd2 (input) intsr2 rxb2 mpien2 cpu mpr2 mpr2 1 rxb2 data 1 (id) rxb2 data 2 (data) 1 ids match. prepares for reception and waits for intsr2. id receive frame data receive frame chapter 15 serial interface uart2 302 user s manual u14260ej3v1ud figure 15-22. timing of receive completion interrupt request in multi-processor transfer mode (2/2) (2) if receive data does not match id d0 start start start stop d7 mpr2 stop mpr2 d0 d7 d0 data 1 (id) ids do not match. ff r x d2 (input) intsr2 rxb2 mpien2 cpu mpr2 mpr2 1 rxb2 data 1 (id) clears mpien2 1 id receive frame data receive frame chapter 15 serial interface uart2 303 user s manual u14260ej3v1ud 15.4.4 infrared data transfer (irda) mode in this mode, pulses can be output, transmitted, or received in the data format of the irda specifications. this mode can be used to transmit or receive data to or from a digital device such as a personal computer. (1) registers to be used asynchronous serial interface mode register 2 (asim2) asynchronous serial interface status register 2 (asis2) baud rate generator control register 2 (brgc2) asynchronous serial interface transmit status register 2 (asif2) clock select register 2 (cksel2) transfer mode specification register 2 (trmc2) port mode register 3 (pm3) port register 3 (p3) the relationship between the register settings and pins is shown below. table 15-11. relationship between register settings and pins (infrared data transfer (irda) mode) asim2 trmc2 pm34 p34 pm35 p35 operation pin function pow txe2 rxe2 ps21 ps20 cl2 sl2 i sem2 trm12 trm02 ismd2 mpien2 mps2 mode p34/ p35/ er2 si3/ so3/ txd2 rxd2 1 0 1 0/1 0/1 0/1 0/1 1 note note 1 reception p34 rxd2 1 1 0 0/1 0/1 0/1 0/1 1 0/1 00 note note transmission txd2 p35 1 1 1 0/1 0/1 0/1 0/1 0/1 1 0/1 001 transmission/ txd2 rxd2 reception note can be set as port function. cautions 1. when using uart2, stop the operation of sio3 (bit 7 (csie3) of serial operation mode register 3 (csim3) = 0). 2. to transfer data in the infrared data transfer (irda) mode, the following conditional expression must be satisfied for the transmit pulse width. (conditional expression) 1.41 s transmit pulse width (set values of tpw20 to tpw23) < transfer rate (set values of mdl20 to mdl27) remark : don t care, asim2: asynchronous serial interface mode register 2, trmc2: transfer mode specification register 2, pm : port mode register, p : port output latch, tpw20 to tpw23: bits 0 to 3 of clock select register 2 (cksel2), mdl20 to mdl27: bits 0 to 7 of baud rate generator control register 2 (brgc2) chapter 15 serial interface uart2 304 user s manual u14260ej3v1ud (2) communication operation (a) data format figure 15-23 shows the format of transmit/receive data. figure 15-23. example of transmit/receive data format in infrared data transfer (irda) mode (1) irda standard format (character bit: 8 bits, parity bit: none, stop bit: 1 bit, communication data: 55h) d0 d1 d2 d3 d4 d5 d6 d7 1 data frame character bit bit time pulse width start bit stop bit (2) other format (character bit: 7 bits, parity bit: even parity, stop bit: 2 bits, communication data: 55h) d0 d1 d2 d3 d4 d5 d6 parity 1 data frame character bit bit time pulse width start bit stop bit chapter 15 serial interface uart2 305 user s manual u14260ej3v1ud one data frame consists of the following bits: start bit .............. 1 bit character bit ...... 7/8 bits (lsb first) parity bit ............. odd/even/0/none stop bit .............. 1/2 bits the character bit length, parity, and stop bit length in one data frame are specified by using asynchronous serial interface mode register 2 (asim2). data is transferred starting from the lsb. the length of the electric pulse transmitted or received in one data frame can be specified by using bits 0 to 3 (tpw20 to tpw23) of clock select register 2 (cksel2). usually, the pulse length is 1.41 s (rated minimum pulse width) to lower the power consumption. the pulse bit rises at the center of a bit cycle. chapter 15 serial interface uart2 306 user s manual u14260ej3v1ud (b) transmission if the infrared data transfer (irda) mode is set by using transfer mode specification register 2 (trmc2) and bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) is set to 1, clock operation is enabled, and the t x d2 pin outputs a low level. if bit 6 (txe2) of asim2 is set to 1 next, transmission is enabled. transmission can be started by writing transmit data to transmit buffer register 2 (txb2). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb2 is transferred to transmit shift register 2 (txs2) and sequentially output to the t x d2 pin, starting from the lsb. if the data to be transmitted next has been written to txb2 by the time transmission is complete, transmitting the next data is started. if no more data has been written to txb2, transmission is stopped until new transmit data is written. figure 15-24 shows the timing of a transmit interrupt. figure 15-24. timing of transmit completion interrupt request in infrared data transfer (irda) mode (1) character bit: 8 bits, parity bit: odd parity, stop bit: 1 bit, communication data: 7dh, trmc2: ismd2 = 0 d0 d1 d2 d3 d4 d5 d6 d7 parity start stop t x d2 (output) intst2 (2) character bit: 8 bits, parity bit: even parity, stop bit: 2 bits, communication data: 9bh, trmc2: ismd2 = 0 d0 start parity stop d1 d2 d3 d4 d5 d6 d7 t x d2 (output) intst2 remark trmc2: transfer mode specification register 2 ismd2: bit 3 of trmc2 chapter 15 serial interface uart2 307 user s manual u14260ej3v1ud (c) reception the interface enters the reception wait status if the infrared data transfer (irda) mode is specified by using transfer mode specification register 2 (trmc2) and bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) is set to 1 and then bit 5 (rxe2) is set to 1. in this status, the r x d2 pin is monitored to detect the start bit. when the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 2 (rx2) at the specified baud rate. when the stop bit is received, the data in rx2 is written to receive buffer register 2 (rxb2). if an overrun error (ove2) occurs, however, the receive data is not written to rxb2 but discarded. even if a parity error (pe2) or framing error (fe2) occurs during reception, reception continues up to the position at which the stop bit is received, and an error interrupt (intsr2/intser2) occurs after completion of reception. figure 15-25. timing of receive completion interrupt request in infrared data transfer (irda) mode d0 start parity stop d1 d2 d3 d4 d5 d6 d7 r x d2 (input) intsr2 rxb2 76h cautions 1. be sure to read receive buffer register 2 (rxb2) even if a reception error has occurred. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. the number of stop bits is always 1 during reception. a second stop bit is ignored. (d) bit rate and pulse width table 15-12 shows the bit rate and pulse width in the infrared data transfer (irda) mode. the rated minimum pulse width is 1.41 s, and the maximum pulse width is the sum of 3/16 of the bit rate and 2.5% of the bit cycle or 1.08 s, whichever is greater. table 15-12. bit rate and pulse width bit rate (bps) allowable bit rate error minimum pulse width nominal value of maximum pulse width (% of bit rate) ( s) 3/16 of pulse width ( s) ( s) 2400 +/ 0.87 1.41 78.13 88.55 9600 19.53 22.13 19200 9.77 11.07 38400 4.88 5.96 57600 3.26 4.34 115200 1.63 2.71 chapter 15 serial interface uart2 308 user s manual u14260ej3v1ud table 15-13. register settings (1/2) notes 1. when using uart2, stop the sio3 operation. 2. can be set as port function. remark : don t care, csim3: serial operation mode register 3, asim2: asynchronous serial interface mode register 2, trmc2: transfer mode specification register 2, pm : port mode register, p : output latch of port asim2 csim3 csie3 0 note 1 power2 0 txe2 0 rxe2 0 ps21 ps20 cl2 sl2 isem2 trm12 trm02 ismd2 mpien2 mps2 p34/si3/txd2 p34 p35/so3/rxd2 p35 pm34 note 2 p34 note 2 pm35 note 2 p35 note 2 pin function operation mode stop trmc2 other than above other than above (1) operation stop mode asim2 csim3 csie3 0 note 1 0 note 1 0 note 1 power2 1 1 1 txe2 0 1 1 rxe2 1 0 1 ps21 0/1 0/1 0/1 ps20 0/1 0/1 0/1 cl2 0/1 0/1 0/1 sl2 0/1 0/1 isem2 0/1 0/1 trm12 0 0 0 trm02 0 0 0 ismd2 0/1 0/1 mpien2 mps2 p34/si3/txd2 p34 txd2 txd2 p35/so3/rxd2 rxd2 p35 rxd2 pm34 note 2 0 0 p34 note 2 0 0 pm35 1 note 2 1 p35 note 2 pin function operation mode receive transmit transmit/receive trmc2 (2) asynchronous serial interface (uart) mode setting prohibited setting prohibited chapter 15 serial interface uart2 309 user s manual u14260ej3v1ud table 15-13. register settings (2/2) notes 1. when using uart2, stop the sio3 operation. 2. can be set as port function. caution when transferring in infrared data transfer (irda) mode, the following conditional expression must be satisfied for spec ification of the transmit pulse width. (conditional expression) 1.41 s transmit pulse width (set values of tpw20 to tpw23 in cksel2 register) < transfer rate (set values of mdl20 to mdl27 in brgc2 register) remark : don t care, csim3: serial operation mode register 3, asim2: asynchronous serial interface mode register 2, trmc2: transfer mode specification register 2, cksel2: clock select register 2, brgc2: baud rate generator control register 2, pm : port mode register, p : output latch of port asim2 csim3 csie3 0 note 1 0 note 1 0 note 1 power2 1 1 1 txe2 0 1 1 rxe2 1 0 1 ps21 0/1 0/1 0/1 ps20 0/1 0/1 0/1 cl2 0/1 0/1 0/1 sl2 0/1 0/1 isem2 0/1 0/1 trm12 0 0 0 trm02 1 1 1 ismd2 0/1 0/1 mpien2 0/1 0/1 0/1 mps2 0/1 0/1 0/1 p34/si3/txd2 p34 txd2 txd2 p35/so3/rxd2 rxd2 p35 rxd2 pm34 note 2 0 0 p34 note 2 0 0 pm35 1 note 2 1 p35 note 2 trmc2 (3) multi-processor transfer mode asim2 power2 1 1 1 txe2 0 1 1 rxe2 1 0 1 ps21 0/1 0/1 0/1 ps20 0/1 0/1 0/1 cl2 0/1 0/1 0/1 sl2 0/1 0/1 isem2 0/1 0/1 trm12 1 1 1 trm02 ismd2 0/1 0/1 mpien2 mps2 p34/si3/txd2 p34 txd2 txd2 p35/so3/rxd2 rxd2 p35 rxd2 pm34 note 2 0 0 p34 note 2 0 0 pm35 1 note 2 1 p35 note 2 trmc2 (4) infrared data transfer (irda) mode pin function other than above other than above csim3 csie3 0 note 1 0 note 1 0 note 1 pin function operation mode receive transmit transmit/receive operation mode receive transmit transmit/receive setting prohibited setting prohibited 310 user? manual u14260ej3v1ud chapter 16 serial interface sio3 serial interface uart2/sio3 can be used in the asynchronous serial interface (uart) mode or 3-wire serial i/o mode. caution do not enable uart2 and sio3 at the same time. 16.1 functions of serial interface sio3 the serial interface sio3 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 16.4.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3), serial output line (so3), and serial input line (si3). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit of the serially transferred 8-bit data is fixed as the msb. 3-wire serial i/o mode can be used when connecting an ic incorporating a clocked serial interface, or a display controller, etc. for details, see 16.4.2 3-wire serial i/o mode . figure 16-1 shows a block diagram of serial interface sio3. figure 16-1. block diagram of serial interface sio3 internal bus 8 selector serial i/o shift register 3 (sio3) si3/t x d2/p34 so3/r x d2/p35 sck3/asck2/p36 intcsi3 f x /2 3 f x /2 4 f x /2 5 output latch serial clock controller serial clock counter interrupt request signal generator chapter 16 serial interface sio3 311 user s manual u14260ej3v1ud 16.2 configuration of serial interface sio3 serial interface sio3 includes the following hardware. table 16-1. configuration of serial interface sio3 item configuration register serial i/o shift register 3 (sio3) interrupt request signal generator serial clock controller control registers serial operation mode register 3 (csim3) port mode register 3 (pm3) port register 3 (p3) (1) serial i/o shift register 3 (sio3) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. when bit 7 (csie3) of serial operation mode register 3 (csim3) is set to 1, a serial operation can be started by writing data to or reading data from sio3. when transmitting, data written to sio3 is output to the serial output (so3). when receiving, data is read from the serial input (si3) and written to sio3. sio3 is set by an 8-bit memory manipulation instruction. reset input makes sio3 undefined. caution do not access sio3 during a transfer operation unless the access is triggered by a transfer start (read operations are disabled when mode3 = 0 and write operations are disabled when mode3 = 1). 16.3 registers to control serial interface sio3 serial interface sio3 is controlled by the following three registers. serial operation mode register 3 (csim3) port mode register 3 (pm3) port register 3 (p3) (1) serial operation mode register 3 (csim3) this register is used to set sio3 s serial clock and operation modes, and to enable/disable operation of sio3. csim3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim3 to 00h. chapter 16 serial interface sio3 312 user s manual u14260ej3v1ud figure 16-2. format of serial operation mode register 3 (csim3) address: ffb8h after reset: 00h r/w symbol 76543210 csim3 csie3 0000 mode3 scl31 scl30 csie3 enable/disable specification for sio3 shift register operation serial counter port 0 operation disabled clear port function note 1 1 operation enabled count operation enabled serial function + port function note 2 mode3 transfer operation modes and flags operation mode transfer start trigger so3/p35/rxd2 pin function 0 transmit/transmit and receive mode write to sio3 so3 1 receive-only mode read from sio3 p35 note 3 scl31 scl30 clock selection f x = 8.38 mhz f x = 12 mhz note 4 0 0 external clock input to sck3 01f x /2 3 1.04 mhz 1.50 mhz 10f x /2 4 523 khz 750 khz 11f x /2 5 261 khz 375 khz notes 1. when csie3 = 0 (sio3 operation stopped status), the si3, so3, and sck3 pins can be used as uart2 or for port functions. 2. when csie3 = 1 (sio3 operation enabled status), the si3 pin can be used as a port pin if only the transmit function is used, and the so3 pin can be used as a port pin if only the receive-only mode is used. 3. when mode3 = 1 (receive-only mode), the so3 pin can be used for port functions. 4. expanded-specification products of pd780078 subseries only. caution do not rewrite the value of csim3 during transfer. however, csie3 can be rewritten using a 1-bit memory manipulation instruction. remark f x : main system clock oscillation frequency chapter 16 serial interface sio3 313 user s manual u14260ej3v1ud (2) port mode register 3 (pm3) pm3 is a register that sets the input/output of port 3 in 1-bit units. to use the p35/so3/rxd2 pin as a serial data output, set pm35 and the output latch of p35 to 0. to use the p34/si3/txd2 pin as a serial data input, and the p36/asck2/sck3 pin as a clock input, set pm34 to 1. at this time, the output latches of p34 and p36 can be either 0 or 1. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 16-3. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n i/o mode selection of p3n pin (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 16 serial interface sio3 314 user s manual u14260ej3v1ud 16.4 operation of serial interface sio3 this section explains the two modes of serial interface sio3. 16.4.1 operation stop mode because serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as normal i/o ports. to set the operation stop mode, clear bit 7 (csie3) of csim3 to 0. (1) register to be used operation stop mode is set by serial operation mode register 3 (csim3). csim3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim3 to 00h. address: ffb8h after reset: 00h r/w symbol 76543210 csim3 csie3 0000 mode3 scl31 scl30 csie3 sio3 operation enable/disable specification shift register operation serial counter port 0 operation disabled clear port function note note when csie3 = 0 (sio3 operation stopped status), the si3, so3, and sck3 pins can be used as uart2 or for port functions. chapter 16 serial interface sio3 315 user s manual u14260ej3v1ud 16.4.2 3-wire serial i/o mode the 3-wire serial i/o mode can be used when connecting a peripheral ic incorporating a clocked serial interface, a display controller, etc. this mode executes communication via three lines: a serial clock line (sck3), serial output line (so3), and serial input line (si3). (1) registers to be used serial operation mode register 3 (csim3) port mode register 3 (pm3) port register 3 (p3) the basic procedure of setting an operation in the 3-wire serial i/o mode is as follows. <1> set bits 2 to 0 (mode3, scl31, and scl30) of the csim3 register (see figure 16-2 ). <2> set bit 7 (csie3) of the csim3 register to 1. transmission/reception is enabled. <3> write data to the sio3 register. data transmission/reception is started. read data from the sio3 register. data reception is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 16-2. relationship between register settings and pins (3-wire serial i/o mode) csim3 pm34 p34 pm35 p35 pm36 p36 operation mode pin function csie3 mode3 scl31 scl30 p34/ p35/ p36/ si3/ so3/ sck3/ txd2 rxd2 asck2 11001 note note 1 slave reception si3 p35 sck3 input 1000 note note 001 slave transmission p34 so3 sck3 input 10001 001 slave transmission/ si3 so3 sck3 reception input 1 1 other 1 note note 0 0 master reception si3 p35 sck3 than above output 10 note note 0000 master transmission p34 so3 sck3 output 10 1 0000 master transmission/ si3 so3 sck3 reception output note can be set as port function. caution when using sio3, stop the operation of uart2 (bit 7 (power2) of asynchronous serial interface mode register 2 (asim2) = 0). remark : don t care, csim3: serial operation mode register 3, pm : port mode register, p : port output latch chapter 16 serial interface sio3 316 user s manual u14260ej3v1ud (2) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set (or read) to serial i/o shift register 3 (sio3). chapter 16 serial interface sio3 317 user s manual u14260ej3v1ud table 16-3. register settings notes 1. when using sio3, stop the uart2 operation. 2. can be set as port function. remark : don t care, asim2: asynchronous serial interface mode register 2, csim3: serial operation mode register 3, pm : port mode register, p : output latch of port asim2 power2 0 note 1 csim3 pm34 note 2 p34 note 2 pm35 note 2 p35 note 2 pm36 note 2 p36 note 2 csie3 0 mode3 scl31 scl30 p34/si3/txd2 p34 p35/so3/rxd2 p35 p36/sck3/asck2 p36 pin function operation mode stop other than above (1) operation stop mode (2) 3-wire serial i/o mode setting prohibited asim2 power2 0 note 1 0 note 1 0 note 1 0 note 1 0 note 1 0 note 1 csim3 pm34 1 note 2 1 1 note 2 1 p34 note 2 note 2 pm35 note 2 0 0 0 0 p35 note 2 0 0 0 0 pm36 1 1 1 0 0 0 p36 0 0 0 csie3 1 1 1 1 1 1 mode3 1 0 0 1 0 0 scl31 0 0 0 scl30 0 0 0 p34/si3/txd2 si3 p34 si3 si3 p34 si3 p35/so3/rxd2 p35 so3 so3 p35 so3 so3 p36/sck3/asck2 sck3 input sck3 input sck3 input sck3 output sck3 output sck3 output pin function other than above other than above setting prohibited operation mode slave receive slave transmit slave transmit/receive master receive master transmit master transmit/receive 318 user? manual u14260ej3v1ud chapter 17 serial interface csi1 17.1 functions of serial interface csi1 serial interface csi1 has the following two modes. (1) operation stop mode this mode is used when serial transfer is not performed. in this mode, the power consumption can be reduced. for details, see 17.4.1 operation stop mode . (2) 3-wire serial i/o mode (msb/lsb-first selectable) this mode is used to transfer 8-bit data by using three lines: a serial clock line (sck1) and two serial data lines (si1 and so1). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode can be used when connecting ics and display controllers having a clocked serial interface. for details, see 17.4.2 3-wire serial i/o mode . 17.2 configuration of serial interface csi1 serial interface csi1 includes the following hardware. table 17-1. configuration of serial interface csi1 item configuration registers transmit buffer register 1 (sotb1) serial i/o shift register 1 (sio1) transmit controller clock start/stop controller & clock phase controller control registers serial operation mode register 1 (csim1) serial clock select register 1 (csic1) port mode register 2 (pm2) port register 2 (p2) chapter 17 serial interface csi1 319 user? manual u14260ej3v1ud figure 17-1. block diagram of serial interface csi1 (1) transmit buffer register 1 (sotb1) this register sets transmit data. transmission is started by writing data to sotb1 when bit 7 (csie1) and bit 6 (trmd1) of serial operation mode register 1 (csim1) are 1. the data written to sotb1 is converted from parallel data into serial data by serial i/o shift register 1, and output to the serial output (so1) pin. sotb1 can be written or read by an 8-bit memory manipulation instruction. reset input makes sotb1 undefined. cautions 1. do not access sotb1 when csot1 = 1 (during serial communication). 2. the ss1 pin can be used in the slave mode. for details of the transmission/reception operation, see 17.4.2 (2) communication operation. (2) serial i/o shift register 1 (sio1) this is an 8-bit register that converts data from parallel into serial or vice versa. the reception status is entered by reading data from sio1 if bit 7 (csie1) of serial operation mode register 1 (csim1) is 1. during reception, data is read from the serial input pin (si1) to sio1. sio1 can be read by an 8-bit memory manipulation instruction. reset input makes sio1 undefined. cautions 1. do not access sio1 when csot1 = 1 (during serial communication). 2. the ss1 pin can be used in the slave mode. for details of the transmission/reception operation, see 17.4.2 (2) communication operation. 17.3 registers to control serial interface csi1 serial interface csi1 is controlled by the following four registers. serial operation mode register 1 (csim1) serial clock select register 1 (csic1) port mode register 2 (pm2) port register 2 (p2) 8 8 8 output latch (p21) pm21 ss1 so1/p21 intcsi1 si1/p20 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 sck1/p22 output selector internal bus serial i/o shift register 1 (sio1) transmit buffer register 1 (sotb1) output latch transmit controller clock start/stop controller & clock phase controller transmit data controller selector chapter 17 serial interface csi1 320 user s manual u14260ej3v1ud (1) serial operation mode register 1 (csim1) this register is used to select the operation mode and enable or disable operation. csim1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1 to 00h. figure 17-2. format of serial operation mode register 1 (csim1) address: ffb0h after reset: 00h r/w note 1 symbol 7 6 5 4 3 2 1 0 csim1 csie1 trmd1 sse1 dir1 0 0 0 csot1 csie1 control of operation in 3-wire serial i/o mode 0 operation disabled note 2 and internal circuit is asynchronously reset note 3 . 1 operation enabled. trmd1 note 4 selection of transmit/receive mode 0 note 5 receive-only mode (transmission disabled). 1 transmit/receive mode sse1 notes 6, 7 specification of whether ss1 pin is used 0 do not use ss1 pin. 1 use ss1 pin. dir1 note 6 specification of first bit 0 msb 1 lsb csot1 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. when using the si1/p20, so1/p21, sck1/p22, and ss1/p80 pins as general-purpose port pins, see caution 2 in figure 17-3 and table 17-2 . 3. bit 0 (csot1) of csim1 and serial i/o shift register 1 (sio1) are reset. 4. do not rewrite trmd1 when csot1 = 1 (during serial communication). 5. the so1 output is fixed to the low level when trmd1 is 0. reception is started when data is read from sio1. 6. do not rewrite these bits when csot1 = 1 (during serial communication). 7. before setting this bit to 1, fix the input level of the ss1 pin to 0 or 1. chapter 17 serial interface csi1 321 user? manual u14260ej3v1ud (2) serial clock select register 1 (csic1) this register is used to specify the data transmission/reception timing and set a serial clock. csic1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csic1 to 10h. figure 17-3. format of serial clock select register 1 (csic1) address: ffb1h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 csic1 0 0 0 ckp1 dap1 cks12 cks11 cks10 ckp1 dap1 specification of data transmission/reception timing type 00 1 01 2 10 3 11 4 cks12 cks11 cks10 csi1 serial clock selection mode f x = 8.38 mhz f x = 12 mhz note 000f x /2 4.19 mhz 6 mhz master mode 001f x /2 2 2.09 mhz 3 mhz 010f x /2 3 1.04 mhz 1.5 mhz 011f x /2 4 523.75 khz 750 khz 100f x /2 5 261.87 khz 375 khz 101f x /2 6 130.94 khz 187.5 khz 110f x /2 7 65.47 khz 93.75 khz 1 1 1 external clock slave mode note expanded-specification products of pd780078 subseries only. d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 si1 input timing d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 si1 input timing d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 si1 input timing d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 si1 input timing chapter 17 serial interface csi1 322 user s manual u14260ej3v1ud cautions 1. do not write to csic1 when csie1 = 1 (operation enabled). 2. when using the p22/sck1 pin as a general-purpose port pin, set ckp1 to 1. 3. the phase type of the data clock is type 3 after reset. remark fx: main system clock oscillation frequency (3) port mode registers 2 and 8 (pm2, pm8) pm2 and pm8 are registers that set input/output of ports 2 and 8 in 1-bit units. when using the p21/so1 pin as a serial data output, set pm21 and the output latch of p21 to 0. when using the p20/si1 pin as a serial data input, the p22/sck1 pin as a clock input, and the p80/ss1 pin as a chip select input, set pm20, pm22, and pm80 to 1. at this time, the output latches of p20, p22, and p80 can be either 0 or 1. pm2 and pm8 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 and pm8 to ffh. figure 17-4. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 17-5. format of port mode register 8 (pm8) address: ff28h after reset: ffh r/w symbol 76543210 pm8 1111111 pm80 pm80 i/o mode selection of p80 pin 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 17 serial interface csi1 323 user s manual u14260ej3v1ud 17.4 operation of serial interface csi1 the following describes the two modes of serial interface csi1. 17.4.1 operation stop mode serial communication is not executed in this mode, so the power consumption can be reduced. in addition, the p20/si1, p21/so1, p22/sck1, and p80/ss1 pins can be used as ordinary i/o port pins in this mode. to set the operation stop mode, clear bit 7 (csie1) of csim1 to 0. (1) register to be used the operation stop mode is set by serial operation mode register 1 (csim1). csim1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1 to 00h. address: ffb0h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csim1 csie1 trmd1 sse1 dir1 0 0 0 csot1 csie1 control of operation in 3-wire serial i/o mode 0 operation disabled note 1 and internal circuit is asynchronously reset note 2 . notes 1. when using the si1/p20, so1/p21, sck1/p22, and ss1/p80 pins as general-purpose port pins, see caution 2 in figure 17-3 and table 17-2 . 2. bit 0 (csot1) of csim1 and serial i/o shift register 1 (sio1) are reset. 17.4.2 3-wire serial i/o mode the 3-wire serial i/o mode can be used when connecting ics and display controllers having a conventional clocked serial interface. in this mode, communication is executed by using three lines: serial clock (sck1), serial output (so1), and serial input (si1) lines. (1) registers to be used serial operation mode register 1 (csim1) serial clock select register 1 (csic1) port mode register 2 (pm2) port register 2 (p2) chapter 17 serial interface csi1 324 user s manual u14260ej3v1ud the basic procedure of setting an operation in the 3-wire serial i/o mode is as follows. <1> set the csic1 register (see figure 17-3 ). <2> set bits 6 to 4 and 0 (trmd1, sse1, dir1, and csot1) of the csim1 register (see figure 17-2 ). <3> set bit 7 (csie1) of the csim1 register to 1. transmission/reception is enabled. <4> write data to the sotb1 register. data transmission/reception is started. read data from the sio1 register. data reception is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 17-2. relationship between register settings and pins (3-wire serial i/o mode) csim1 pm20 p20 pm21 p21 pm22 p22 pm80 p80 operation pin function csie1 trmd1 sse1 dir1 mode p20/ p21/ p22/ p80/ si1 so1 sck1 ss1 1000/11 note 1 note 1 1 note 1 note 1 slave si1 p21 sck1 p80 11 reception note 2 input note 2 ss1 1100/1 note 1 note 1 001 note 1 note 1 slave p20 so1 sck1 p80 11 transmission note 2 input note 2 ss1 1100/11 001 note 1 note 1 slave si1 so1 sck1 p80 11 transmission/ input note 2 ss1 reception note 2 1000/11 note 1 note 1 1 note 1 note 1 master si1 p21 sck1 p80 reception output 1100/1 note 1 note 1 001 note 1 note 1 master p20 so1 sck1 p80 transmission output 1100/11 001 note 1 note 1 master si1 so1 sck1 p80 transmission/ output reception notes 1. can be set as port function. 2. to use the slave mode, set cks12, cks11, and cks10 to 1, 1, 1. remark : don t care, csim1: serial operation mode register 1, cks12, cks11, cks10: bits 2 to 0 of serial clock select register 1 (csic1) chapter 17 serial interface csi1 325 user s manual u14260ej3v1ud (2) communication operation in the 3-wire serial i/o mode, data is transmitted or received in 8-bit units. each bit of data is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1) of serial operation mode register 1 (csim1) is 1. transmission/reception is started when a value is written to transmit buffer register 1 (sotb1). data can be received when bit 6 (trmd1) of serial operation mode register 1 (csim1) is 0. reception is started when data is read from serial i/o shift register 1 (sio1). however, if bit 5 (sse1) of csim1 is set to 1 in slave mode, the operation is as follows. <1> low level input to the ss1 pin transmission/reception is started when sotb1 is written, or reception is started when sio1 is read. <2> high level input to the ss1 pin transmission/reception or reception is held, therefore, even if sotb1 is written or sio1 is read, transmission/reception or reception will not be started. <3> data is written to sotb1 or data is read from sio1 while a high level is input to the ss1 pin, then a low level is input to the ss1 pin transmission/reception or reception is started. <4> a high level is input to the ss1 pin during transmission/reception or transmission transmission/reception or reception is suspended. after communication has been started, bit 0 (csot1) of csim1 is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif1) is set, and csot1 is cleared to 0. then the next communication is enabled. cautions 1. do not access the control register and data register when csot1 = 1 (during serial communication). 2. when bit 5 (sse1) of csim1 is set to 1 in slave mode, input a low level to the ss1 pin one clock or more before the clock operation starts. chapter 17 serial interface csi1 326 user s manual u14260ej3v1ud figure 17-6. timing of 3-wire serial i/o mode (1/2) (1) transmission/reception timing (type 1; trmd1 = 1, dir1 = 0, ckp1 = 0, dap1 = 0, sse1 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1. ss1 note sck1 read/write trigger sotb1 sio1 csot1 intcsi1 csiif1 so1 si1 (receives aah) note the sse1 flag and ss1 pin are used in the slave mode. chapter 17 serial interface csi1 327 user s manual u14260ej3v1ud figure 17-6. timing of 3-wire serial i/o mode (2/2) (2) transmission/reception timing (type 2; trmd1 = 1, dir1 = 0, ckp1 = 0, dap1 = 1, sse1 = 1 note ) abh 56h adh 5ah b5h 6ah d5h 55h is written to sotb1. ss1 note sck1 sotb1 read/write trigger sio1 csot1 intcsi1 csiif1 so1 aah 55h (communication data) si1 (inputs aah) note the sse1 flag and ss1 pin are used in the slave mode. chapter 17 serial interface csi1 328 user s manual u14260ej3v1ud figure 17-7. timing of clock/data phase (a) type 1; ckp1 = 0, dap1 = 0 (b) type 2; ckp1 = 0, dap1 = 1 (c) type 3; ckp1 = 1, dap1 = 0 (d) type 4; ckp1 = 1, dap1 = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 writing to sotb1 or reading from sio1 si1 capture csiif1 csot1 d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 writing to sotb1 or reading from sio1 si1 capture csiif1 csot1 d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 writing to sotb1 or reading from sio1 si1 capture csiif1 csot1 d7 d6 d5 d4 d3 d2 d1 d0 sck1 so1 writing to sotb1 or reading from sio1 si1 capture csiif1 csot1 chapter 17 serial interface csi1 329 user s manual u14260ej3v1ud (3) timing of output to so1 pin (first bit) when communication is started, the value of transmit buffer register 1 (sotb1) is output from the so1 pin. the following describes the output operation of the first bit at this time. figure 17-8. output operation of first bit (1) ckp1 = 0, dap1 = 0 (or ckp1 = 1, dap1 = 0) the first bit is directly latched to the output latch from the sotb1 register at the falling (or rising) edge of sck1, passed through the output selector and output from the so1 pin. the value of the sotb1 register is transferred to the sio1 register at the next rising (or falling) edge of sck1 and the data shifts by one bit. simultaneously, the first bit of the received data is passed through the si1 pin and stored in the sio1 register. the second and subsequent bits are latched to the output latch at the next falling (or rising) edge of sck1 and the respective data is output from the so1 pin. (2) ckp1 = 0, dap1 = 1 (or ckp1 = 1, dap1 = 1) the first bit is output from the so1 pin directly from the sotb1 register through the output selector at the falling edge of the write signal of sotb1 or the read signal of the sio1 register. the value of the sotb1 register is transferred to the sio1 register at the next falling (or rising) edge of sck1 and shifts by one bit. simultaneously, the first bit of the received data is stored in the sio1 register through the si1 pin. the second and subsequent bits are latched to the output latch from sio1 at the next rising (or falling) edge of sck1 and the data is output from the so1 pin. sck1 sotb1 sio1 output latch so1 writing to sotb1 or reading from sio1 first bit 2nd bit first bit 2nd bit 3rd bit sck1 sotb1 sio1 output latch so1 writing to sotb1 or reading from sio1 chapter 17 serial interface csi1 330 user s manual u14260ej3v1ud (4) output value of so1 pin (last bit) after communication has been completed, the so1 pin holds the output value of the last bit. figure 17-9. output value of so1 pin (last bit) (1) type 1; ckp1 = 0 and dap1 = 0 (or ckp1 = 1, dap1 = 0) (2) type 2; ckp1 = 0 and dap1 = 1 (or ckp1 = 1, dap1 = 1) sck1 sotb1 sio1 so1 output latch writing to sotb1 or reading from sio1 ( next request is issued.) last bit sck1 sotb1 sio1 so1 output latch writing to sotb1 or reading from sio1 ( next request is issued.) last bit chapter 17 serial interface csi1 331 user s manual u14260ej3v1ud (5) so1 output the status of the so1 output is as follows if bit 7 (csie1) of serial operation mode register 1 (csim1) is cleared to 0. table 17-3. so1 output status trmd1 dap1 dir1 so1 output note 1 trmd1 = 0 note 2 low-level output note 2 trmd1 = 1 dap1 = 0 so1 latch value (low-level output) dap1 = 1 dir1 = 0 bit 7 value of sotb1 dir1 = 1 bit 0 value of sotb1 notes 1. the pm21, p21, and sse1 bits and the ss1 pin must also be set to actually produce an output from the so1/p21 pin. 2. status after reset caution if a value is written to the trmd1, dap1, and dir1 bits, the output value of the so1 bit changes. chapter 17 serial interface csi1 332 user s manual u14260ej3v1ud table 17-4. register settings note can be set as port function. remark : don t care, csim1: serial operation mode register 1, csic1: serial clock select register 1, pm : port mode register, p : output latch of port csim1 csie1 0 trmd1 0 sse1 dir1 ckp1 1 dap1 0 cks12 0 cks11 0 cks10 0 pm20 note p20 note pm21 note p21 note pm22 note p22 note p21/so1 p21 p20/si1 p20 p22/sck1 p22 pin function operation mode stop csic1 (1) operation stop mode (2) 3-wire serial i/o mode setting prohibited other than above csim1 csie1 1 1 1 1 1 1 trmd1 0 1 1 0 1 1 sse1 dir1 0/1 0/1 0/1 0/1 0/1 0/1 ckp1 0/1 0/1 0/1 0/1 0/1 0/1 dap1 0/1 0/1 0/1 0/1 0/1 0/1 cks12 1 1 1 cks11 1 1 1 cks10 1 1 1 pm20 1 note 1 1 note 1 p20 note note pm21 note 0 0 note 0 0 p21 note 0 0 note 0 0 pm22 1 1 1 0 0 0 p22 0 0 0 p21/so1 p21 so1 so1 p21 so1 so1 p20/si1 si1 p20 si1 si1 p20 si1 p22/sck1 sck1 input sck1 input sck1 input sck1 output sck1 output sck1 output pin function operation mode slave receive slave transmit slave transmit/receive master receive master transmit master transmit/receive csic1 setting prohibited other than above other than above 333 user? manual u14260ej3v1ud chapter 18 serial interface iic0 ( pd780078y subseries only) 18.1 functions of serial interface iic0 serial interface iic0 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. the transfer rate is as follows. 97.5 khz (standard mode) or 350 khz (high-speed mode): when operated at f x = 8.38 mhz this mode complies with the i 2 c bus format and can output ?tart condition? ?ata? and ?top condition?data segments when transmitting via the serial data bus. these data segments are automatically detected by hardware during reception. since scl0 and sda0 are open-drain outputs, the iic0 requires pull-up resistors for the serial clock line (scl0) and the serial data bus line (sda0). figure 18-1 shows a block diagram of serial interface iic0. 334 chapter 18 serial interface iic0 ( pd780078y subseries only) user? manual u14260ej3v1ud figure 18-1. block diagram of serial interface iic0 internal bus slave address register 0 (sva0) noise eliminator sda0/p32 iic shift register 0 (iic0) ack detector pm32 output latch (p32) start condition detector stop condition detector serial clock counter serial clock controller noise eliminator scl0/p33 n-ch open -drain output prescaler n-ch open -drain output internal bus f x serial clock wait controller cld0 dad0 smc0 dfc0 cl00 interrupt request signal generator wake-up controller ack output circuit data hold time correction circuit cl00 dq so0 latch set clear match signal iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 adkd0 std0 spd0 iic transfer clock select register 0 (iiccl0) intiic0 iic status register 0 (iics0) iic control register 0 (iicc0) pm33 output latch (p33) 335 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-2 shows a serial bus configuration example. figure 18-2. serial bus configuration example using i 2 c bus sda0 scl0 sda0 +v dd0 +v dd0 scl0 sda0 scl0 slave cpu3 address 2 sda0 scl0 slave ic address 3 sda0 scl0 slave ic address n serial data bus serial clock master cpu2 slave cpu2 address 1 master cpu1 slave cpu1 address 0 336 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.2 configuration of serial interface iic0 serial interface iic0 includes the following hardware. table 18-1. configuration of serial interface iic0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic transfer clock select register 0 (iiccl0) port mode register 3 (pm3) port register 3 (p3) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. iic0 can be used for both transmission and reception. write and read operations to iic0 are used to control the actual transmit and receive operations. iic0 is set by an 8-bit memory manipulation instruction. reset input clears iic0 to 00h. figure 18-3. format of iic shift register 0 (iic0) address: ff1fh after reset: 00h r/w symbol 76543210 iic0 caution do not write data to iic0 during data transfer. (2) slave address register 0 (sva0) this register sets local addresses when in slave mode. sva0 is set by an 8-bit memory manipulation instruction. reset input clears sva0 to 00h. figure 18-4. format of slave address register 0 (sva0) address: ffabh after reset: 00h r/w symbol 76543210 sva0 0 note note bit 0 is fixed to 0. 337 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud (3) so0 latch the so0 latch is used to retain the sda0 pin s output level. (4) wake-up controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt request is generated by the following two triggers. falling edge of eighth or ninth clock of the serial clock (set by wtim0 bit note ) interrupt request generated when a stop condition is detected (set by spie0 bit note ) note wtim0 bit: bit 3 of iic control register 0 (iicc0) spie0 bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock. 338 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.3 registers to control serial interface iic0 serial interface iic0 is controlled by the following five registers. iic control register 0 (iicc0) iic status register 0 (iics0) iic transfer clock select register 0 (iiccl0) port mode register 3 (pm3) port register 3 (p3) (1) iic control register 0 (iicc0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears iicc0 to 00h. 339 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-5. format of iic control register 0 (iicc0) (1/4) address: ffa8h after reset: 00h r/w symbol 76543210 iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable 0 stop operation. reset iic status register 0 (iics0). stop internal operation. 1 enable operation. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) cleared by instruction set by instruction when reset is input lrel0 exit from communications 0 normal operation 1 this exits from the current communications operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines go into the high impedance state. the following flags of iic status register 0 (iics0) and iic control register 0 (iicc0) are cleared. std0 ackd0 trc0 coi0 exc0 msts0 stt0 spt0 the standby mode following exit from communications remains in effect until the following communications entry conditions are met. after a stop condition is detected, restart is in master mode. an address match or extension code reception occurs after the start condition. condition for clearing (lrel0 = 0) note condition for setting (lrel0 = 1) automatically cleared after execution set by instruction when reset is input wrel0 cancel wait 0 do not cancel wait. 1 cancel wait. this setting is automatically cleared after wait is canceled. when wrel0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (trc0 = 1), the sda0 line goes into the high impedance state (trc0 = 0). condition for clearing (wrel0 = 0) note condition for setting (wrel0 = 1) automatically cleared after execution set by instruction when reset is input spie0 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 = 0) note condition for setting (spie0 = 1) cleared by instruction set by instruction when reset is input note this flag s signal is invalid when iice0 = 0. 340 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-5. format of iic control register 0 (iicc0) (2/4) wtim0 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device . this bit s setting is invalid during an address transfer and is valid after the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) note condition for setting (wtim0 = 1) cleared by instruction set by instruction when reset is input acke0 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during the ninth clock period, the sda0 line is set to low level. however, the ack is invalid during address transfers and is valid when exc0 = 1. condition for clearing (acke0 = 0) note condition for setting (acke0 = 1) cleared by instruction set by instruction when reset is input note this flag s signal is invalid when iice0 = 0. 341 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-5. format of iic control register 0 (iicc0) (3/4) stt0 start condition trigger 0 do not generate a start condition. 1 when bus is released (during stop mode): generate a start condition (for starting as master). the sda0 line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level. when bus is not used: this trigger functions as a start condition reservation flag. when set, it releases the bus and then automatically generates a start condition. wait status (during master mode): generate a restart condition after wait is released. cautions concerning set timing for master reception: cannot be set during transfer. can be set only in the waiting period when acke0 has been set to 0 and slave has been notified of final reception. for master transmission: a start condition may not be generated normally during the ack period. therefore, set it during the waiting period. cannot be set at the same time as spt0. condition for clearing (stt0 = 0) condition for setting (stt0 = 1) cleared by loss in arbitration set by instruction cleared after start condition is generated by master device cleared by lrel0 = 1 (exit from communications) when iice0 = 0 (operation stop) when reset is input remark bit 1 (stt0) is 0 when read after data has been set. 342 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-5. format of iic control register 0 (iicc0) (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0 line changes from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set during transfer. can be set only in the waiting period when acke0 has been set to 0 and slave has been notified of final reception. for master transmission: a stop condition cannot be generated normally during the ack0 period. therefore, set it during the waiting period. cannot be set at the same time as stt0. spt0 can be set only when in master mode. note when wtim0 has been set to 0, if spt0 is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high level period of the ninth clock. when a ninth clock must be output, wtim0 should be changed from 0 to 1 during the wait period following output of eight clocks, and spt0 should be set during the wait period that follows output of the ninth clock. condition for clearing (spt0 = 0) condition for setting (spt0 = 1) cleared by loss in arbitration set by instruction automatically cleared after stop condition is detected cleared by lrel0 = 1 (exit from communications) when iice0 = 0 (operation stop) when reset is input note set spt0 only in master mode. however, spt0 must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 18.5.14 other cautions . caution when bit 3 (trc0) of iic status register 0 (iics0) is set to 1, wrel0 is set during the ninth clock and wait is canceled, after which trc0 is cleared and the sda0 line is set to high impedance. remark bit 0 (spt0) becomes 0 when it is read after data setting. 343 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud (2) iic status register 0 (iics0) this register indicates the status of i 2 c. iics0 is read by a 1-bit or 8-bit memory manipulation instruction. reset input clears iics0 to 00h. figure 18-6. format of iic status register 0 (iics0) (1/3) address: ffa9h after reset: 00h r symbol 76543210 iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) when a stop condition is detected when a start condition is generated when ald0 = 1 (arbitration loss) cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when reset is input ald0 detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a win . 1 this status indicates the arbitration result was a loss . msts0 is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) automatically cleared after iics0 is read note when the arbitration result is a loss . when iice0 changes from 1 to 0 (operation stop) when reset is input exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) when a start condition is detected when the higher 4 bits of the received when a stop condition is detected address data are either 0000 or 1111 cleared by lrel0 = 1 (exit from communications) (set at the rising edge of the eighth clock). when iice0 changes from 1 to 0 (operation stop) when reset is input note this register is also cleared when a bit manipulation instruction is executed for bits other than iics0. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) 344 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-6. format of iic status register 0 (iics0) (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) when a start condition is detected when the received address matches the local when a stop condition is detected address (slave address register 0 (sva0)) cleared by lrel0 = 1 (exit from communications) (set at the rising edge of the eighth clock). when iice0 changes from 1 to 0 (operation stop) when reset is input trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set to high impedance. 1 transmit status. the value in the so0 latch is enabled for output to the sda0 line (valid starting at the falling edge of the first byte s ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) 345 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-6. format of iic status register 0 (iics0) (3/3) ackd0 detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) when a stop condition is detected after the sda0 line is set to low level at the at the rising edge of the next byte s first clock rising edge of the scl0 s ninth clock cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when reset is input std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std0 = 0) condition for setting (std0 = 1) when a stop condition is detected when a start condition is detected at the rising edge of the next byte s first clock following address transfer cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when reset is input spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device s communication was terminated and the bus was released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) at the rising edge of the address transfer byte s when a stop condition is detected first clock following setting of this bit and detection of a start condition when iice0 changes from 1 to 0 (operation stop) when reset is input remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0) 346 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud (3) iic transfer clock select register 0 (iiccl0) this register is used to set the transfer clock for the i 2 c bus. iiccl0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears iiccl0 to 00h. figure 18-7. format of iic transfer clock select register 0 (iiccl0) (1/2) address: ffaah after reset: 00h r/w note symbol 76543210 iiccl0 0 0 cld0 dad0 smc0 dfc0 0 cl00 cld0 detection of scl0 line level (valid only when iice0 = 1) 0 scl0 line was detected at low level. 1 scl0 line was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) when the scl0 line is at low level when the scl0 line is at high level when iice0 = 0 (operation stop) when reset is input dad0 detection of sda0 line level (valid only when iice0 = 1) 0 sda0 line was detected at low level. 1 sda0 line was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) when the sda0 line is at low level when the sda0 line is at high level when iice0 = 0 (operation stop) when reset is input smc0 operation mode switching 0 operation in standard mode 1 operation in high-speed mode condition for clearing (smc0 = 0) condition for setting (smc0 = 1) cleared by instruction set by instruction when reset is input note bits 4 and 5 are read-only bits. remark iice0: bit 7 of iic control register 0 (iicc0) 347 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-7. format of iic transfer clock select register 0 (iiccl0) (2/2) dfc0 control of digital filter operation note 1 0 digital filter off 1 digital filter on cl00 selection of transfer rate standard mode high-speed mode f x = 8.38 mhz f x = 8.38 mhz 0f x /44 190.4 khz note 2 f x /24 350 khz 1f x /86 97.5 khz notes 1. the digital filter can be used when in high-speed mode. the response time is slower when the digital filter is used. 2. the transfer rate in standard mode must not be set when f x is more than 100 khz. caution stop serial transfer once before rewriting cl00 to other than the same value. remarks 1. f x : main system clock oscillation frequency 2. the transfer clock does not change in the high-speed mode even if dfc0 is turned on and off. (4) port mode register 3 (pm3) pm3 is a register that set the input/output of port 3 in 1-bit units. to use the p32/sda0 pin as serial data i/o and the p33/scl0 pin as clock i/o, set pm32 and pm33, and the output latches of p32 and p33 to 0. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 18-8. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n i/o mode selection of p3n pin (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off) 348 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.4 i 2 c bus mode functions 18.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0 this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull- up resistor is required. figure 18-9. pin configuration diagram v dd0 v ss0 v ss0 v ss0 v ss0 scl0 sda0 scl0 sda0 v dd0 clock output master device (clock input) data output data input (clock output) clock input data output data input slave device 349 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus s serial data communication format and the signals used by the i 2 c bus. figure 18-10 shows the transfer timing for the start condition , data , and stop condition output via the i 2 c bus s serial data bus. figure 18-10. i 2 c bus serial data transfer timing the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. however, in the slave device, the scl0 s low level period can be extended and a wait can be inserted. 18.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signals that the master device outputs to the slave device when starting a serial transfer. when the device is used as a slave, start conditions can be detected. figure 18-11. start conditions a start condition is output when bit 1 (stt0) of iic control register 0 (iicc0) is set (to 1) after a stop condition has been detected (spd0: bit 0 = 1 in iic status register 0 (iics0)). when a start condition is detected, bit 1 (std0) of iics0 is set (to 1). 1-7 8 9 1-7 8 9 1-7 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack h scl0 sda0 350 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register 0 (sva0). if the address data matches the sva0 values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 18-12. address note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 transfer direction specification below, are together written to iic shift register 0 (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0. 18.5.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0 , it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1 , it indicates that the master device is receiving data from a slave device. figure 18-13. transfer direction specification note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. address scl0 1 sda0 intiic0 note 23456789 a6 a5 a4 a3 a2 a1 a0 r/w scl0 1 sda0 intiic0 23456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note 351 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.4 acknowledge (ack) signal the acknowledge (ack) signal is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sda0 line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acke0) of iic control register 0 (iicc0) is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes bit 3 (trc0) of iic status register 0 (iics0) to be set. when this trc0 bit s value is 0 , it indicates receive mode. therefore, acke0 should be set to 1. when the slave device is receiving (when trc0 = 0), if the slave devices does not need to receive any more data after receiving several bytes, setting acke0 to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trc0 = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acke0 to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda0 line (i.e., stops transmission) during transmission from the slave device. figure 18-14. ack signal when the local address is received, an ack signal is automatically output in sync with the falling edge of the scl0 s eighth clock regardless of the acke0 value. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: ack signal is output when acke0 is set to 1 before wait cancellation. (wtim0 = 0) when 9-clock wait is selected: ack signal is automatically output at the falling edge of the scl0 s eighth clock (wtim0 = 1) if acke0 has already been set to 1. scl0 1 sda0 23456789 a6 a5 a4 a3 a2 a1 a0 r/w ack 352 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 18-15. stop condition a stop condition is generated when bit 0 (spt0) of iic control register 0 (iicc0) is set (to 1). when the stop condition is detected, bit 0 (spd0) of iic status register 0 (iics0) is set (to 1) and intiic0 is generated when bit 4 (spie0) of iicc0 is set (to 1). h scl0 sda0 353 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.6 wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave devices, the next data transfer can begin. figure 18-16. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke0 = 1) scl0 6 sda0 78 9 123 scl0 iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iic0 data write (cancel wait) slave wait after output of eighth clock wait signal from slave wait signal from master ffh is written to iic0 or wrel0 is set to 1 transfer lines 354 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-16. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke0 = 1) remark acke0: bit 2 of iic control register 0 (iicc0) wrel0: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated depending on the setting of bit 3 (wtim0) of iic control register 0 (iicc0). normally, the receiving side cancels the wait status when bit 5 (wrel0) of iicc0 is set to 1 or when ffh is written to iic shift register 0 (iic0), and the transmitting side cancels the wait status when data is written to iic0. the master device can also cancel the wait status via either of the following methods. by setting bit 1 (stt0) of iicc0 to 1 by setting bit 0 (spt0) of iicc0 to 1 scl0 6 sda0 789 123 scl0 iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master and slave both wait after output of ninth clock iic0 data write (cancel wait) slave ffh is written to iic0 or wrel0 is set to 1 output according to previously set acke0 value transfer lines wait signal from master and slave wait signal from slave 355 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.7 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) of iic control register 0 (iicc0) determines the timing by which intiic0 is generated and the corresponding wait control, as shown in table 18-2. table 18-2. intiic0 generation timing and wait control wtim0 during slave device operation during master device operation address data reception data transmission address data reception data transmission 09 notes 1, 2 8 note 2 8 note 2 988 19 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave device s intiic0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (sva0). at this point, ack is output regardless of the value set to iicc0 s bit 2 (acke0). for a slave device that has received an extension code, intiic0 occurs at the falling edge of the eighth clock. however, if the address does not match after restart, intiic0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. if the received address does not match the contents of slave address register 0 (sva0) and extension code is not received, neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of the serial clock s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception slave device operation: interrupt and wait timing are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim0 bit. master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. by setting bit 5 (wrel0) of iic control register 0 (iicc0) to 1 by writing to iic shift register 0 (iic0) by setting a start condition (setting bit 1 (stt0) of iicc0 to 1) note by setting a stop condition (setting bit 0 (spt0) of iicc0 to 1) note note master only. when an 8-clock wait has been selected (wtim0 = 0), the output level of ack must be determined prior to wait cancellation. 356 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud (5) stop condition detection intiic0 is generated when a stop condition is detected (only when spie0 = 1). 18.5.8 address match detection method in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match can be detected automatically by hardware. an interrupt request (intiic0) occurs when a local address has been set to slave address register 0 (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 18.5.9 error detection in i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 18.5.10 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111 , the extension code reception flag (exc0) is set for extension code reception and an interrupt request (intiic0) is issued at the falling edge of the eighth clock. the local address stored in slave address register 0 (sva0) is not affected. (2) if 111110 is set to sva0 by a 10-bit address transfer and 111110 is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. higher four bits of data match: exc0 = 1 note seven bits of data match: coi0 = 1 note note exc0: bit 5 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, you can set bit 6 (lrel0) of iic control register 0 (iicc0) to 1 to set the standby mode for the next communication operation. table 18-3. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 cbus address 0000 010 address that is reserved for different bus format 1111 0 10-bit slave address specification 357 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.11 arbitration when several master devices simultaneously output a start condition (when stt0 is set to 1 before std0 is set to 1 note ), communication among the master devices is performed as the number of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald0) in iic status register 0 (iics0) is set (1) via the timing by which the arbitration loss occurred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 18.5.16 timing of i 2 c interrupt request (intiic0) occurrence . note std0: bit 1 of iic status register 0 (iics0) stt0: bit 1 of iic control register 0 (iicc0) figure 18-17. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z 358 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud table 18-4. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data transmission when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when spie0 = 1) note 2 when data is at low level while attempting to output a at falling edge of eighth or ninth clock following byte transfer note 1 restart condition when stop condition is detected while attempting to when stop condition is output (when spie0 = 1) note 2 output a restart condition when data is at low level while attempting to output a at falling edge of eighth or ninth clock following byte transfer note 1 stop condition when scl0 is at low level while attempting to output a restart condition notes 1. when wtim0 (bit 3 of iic control register 0 (iicc0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension code s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that arbitration will occur, set spie0 = 1 for master device operation. remark spie0: bit 4 of iic control register 0 (iicc0) 18.5.12 wake-up function the i 2 c bus slave function is a function that generates an interrupt request (intiic0) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wake-up standby mode is set. this wake-up standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 4 (spie0) of iic control register 0 (iicc0) is set regardless of the wake-up function, and this determines whether interrupt requests are enabled or disabled. 359 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.13 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. when arbitration results in neither master nor slave operation when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iic control register 0 (iicc0) was set to 1). if bit 1 (stt0) of iicc0 is set (1) while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait status is set. when the bus release is detected (when a stop condition is detected), writing to iic shift register 0 (iic0) causes the master address transfer to start. at this point, bit 4 (spie0) of iicc0 should be set (1). when stt0 has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been released ........................................... a start condition is generated if the bus has not been released (standby mode) .......... communication reservation check whether the communication reservation operates or not by using msts0 (bit 7 of iic status register 0 (iics0)) after sst0 is set and the wait time elapses. the wait periods, which should be set via software, are listed in table 18-5. these wait periods can be set via the settings for bits 3 and 0 (smc0 and cl00) in iic transfer clock select register 0 (iiccl0). table 18-5. wait periods smc0 cl00 wait period 0 0 26 clocks 0 1 46 clocks 1 0 16 clocks 11 figure 18-18 shows the communication reservation timing. 360 chapter 18 serial interface iic0 ( pd780078y subseries only) user? manual u14260ej3v1ud figure 18-18. communication reservation timing remark iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after bit 1 (std0) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of iic control register 0 (iicc0) to 1 before a stop condition is detected. figure 18-19. timing for accepting communication reservations figure 18-20 shows the communication reservation protocol. scl0 sda0 std0 spd0 standby mode 2 13456 2 13456 789 scl0 sda0 stt0 = 1 program processing hardware processing write to iic0 set spd0 and intiic0 communication reservation set std0 output by master with bus mastership 361 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-20. communication reservation protocol note the communication reservation operation executes a write to iic shift register 0 (iic0) when a stop condition interrupt request occurs. remark stt0: bit 1 of iic control register 0 (iicc0) msts0: bit 7 of iic status register 0 (iics0) iic0: iic shift register 0 18.5.14 other cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. (a) set iic transfer clock select register 0 (iiccl0). (b) set (1) bit 7 (iice0) of iic control register 0 (iicc0). (c) set (1) bit 0 (spt0) of iicc0. di set1 stt0 define communication reservation wait cancel communication reservation no yes mov iic0, # h ei msts0 = 0? (communication reservation) note (generate start condition) sets stt0 flag (communication reservation) secures wait period set by software (see table 18-5 ). confirmation of communication reservation clear user flag iic0 write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram) 362 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud 18.5.15 communication operations (1) master operations the procedure of controlling slave eeprom tm using the pd780078y subseries as the master of the i 2 c bus is as follows. figure 18-21. master operation flowchart (1/5) issue start condition. stt0 = 1 set transfer clock. iiccl0 h set port (mode and data). pm32, pm33 1, p32, p33 0 set port. pm32, pm33 0 set iic control register 0. iice0 = wtim0 = 1 issue stop condition. spt0 = 1 set interrupt. iicif0, iicmk0 0 spd0 = 1? a start no yes first perform initialization to use i 2 c. set the port that functions alternately as the pins to be used. first set the port in the input mode, and clear the output latch to 0. specify the operation mode, turn on/off the digital filter, and specify the transfer rate. set a 9-clock wait and enable operation. set the port in the output mode to enable output of i 2 c. clear the interrupt request of i 2 c. clear the mask to enable the interrupt when using the interrupt. issue the stop condition before starting operation, and release the bus. wait until the bus is released. if the stop condition is detected, the bus is released and can be used. declare use of the bus by issuing the start condition. if the stop condition cannot be detected, the chances are the connected pin is driving the bus low. in this case, refer to remark . 363 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-21. master operation flowchart (2/5) ackd0 = 1? transmit eeprom higher address. iic0 eeprom higher address transmit eeprom lower address. iic0 eeprom lower address transfer slave address. iic0 address, r/w (0) intiic0 = 1? clear intiic0. clear intiic0. b ackd0 = 1? end (no slave) no no no end (no acknowledgment) a std0 = 1? no yes yes yes yes yes intiic0 = 1? no wait until the start condition is detected and the bus is ready. specify writing and transfer the address of the slave (eeprom). wait until transfer is completed. clear intiic0 to poll intiic0 without using an interrupt. if ack is not sent, it means that the specified slave does not exist. end processing. if a slave does exist, divide the address of eeprom (2 bytes) into two, and start transmitting the address from the higher byte. each time transmission is completed, check ack. transmit the lower address. 364 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-21. master operation flowchart (3/5) ackd0 = 1? transmission? trc0 = 1? transmit write data. iic0 data prepare write data. intiic0 = 1? clear intiic0. clear intiic0. b reception c ackd0 = 1? transfer end? end end (no acknowledgment) set error flag. no no no no no intiic0 = 1? yes yes yes yes yes yes when writing data to eeprom, continue writing data. when reading data from eeprom, start reception processing. prepare data to be written to eeprom, and transmit it to eeprom. each time data has been transmitted, the slave returns ack. if any error occurs before transmission of the necessary data is completed, ack may not be returned. in this case, end transfer. in the case of an error, set the error flag as shown on the left, and release the bus. 365 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud figure 18-21. master operation flowchart (4/5) transfer slave address. iic0 address, r/w (1) issue stop condition. spt0 = 1 intiic0 = 1? clear intiic0. d reception ackd0 = 1? end no issue start condition. stt0 = 1 std0 = 1? no no end (no acknowledgment) when transmission is completed, issue the stop condition to notify the slave of completion of transmission. for reception, the data transfer direction must be changed. issue the start condition again and redo (restart) communication. because the master receives data this time, set the r/w bit to 1 and transmit an address. c spd0 = 1? no yes yes yes yes 366 chapter 18 serial interface iic0 ( pd780078y subseries only) user? manual u14260ej3v1ud figure 18-21. master operation flowchart (5/5) remark while the slave is outputting a low level to the data line, the master cannot issue the stop condition. this happens if eeprom is not reset, even though the microcontroller is reset, because of supply voltage fluctuation during communication (reading from eeprom). in this case, the eeprom continues sending data, and may output a low level to the data line. because the structure of i 2 c does not allow the master to forcibly make the data line high, the master cannot issue the stop condition. to avoid this phenomenon, it is possible to use a clock line as a port, output a dummy clock from the port, continue reading data from eeprom by inputting the dummy clock, and complete reading with some eeproms (because the data line goes high when reading is completed, the master can issue the stop condition. after that, the status of eeprom can be controlled). at this time, the port corresponding to the data line must always be in the high-impedance state (high-level output). re-set iic control register 0. acke0 = 1, wtim0 = 0 issue stop condition. spt0 = 1 re-set iic control register 0. acke0 = 0, wrel0 = wtim0 = 1 spd0 = 1? d end no remaining data? yes start data reception. iic0 0ffh intiic0 = 1? no no set so that ack is automatically returned after an 8-clock wait (set acke0 so that ack is returned except when the last data is received. specify an 8-clock wait so that automatic returning of ack can be cleared when the last data is received). write dummy data to iic0 and start reception (reception can also be started when wrel0 = 1). reception is completed when intiic0 occurs. save the received data to a buffer. when reception of data is completed, disable automatic returning of ack, set a 9- clock wait, cancel wait in the ack cycle, and stop at the 9th clock. as a result, ack is not returned to the slave. this indicates the completion of reception. issue the stop condition and end communication. save receive data. clear intiic0. yes yes intiic0 = 1? no yes 367 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud (2) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefore, processing by the intiic0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. in the following explanation, it is assumed that the extension code is not supported for data communication. it is also assumed that the intiic0 interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of intiic0. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data communication is performed (from valid address detection to stop condition detection, no detection of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiic0 interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communication is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communication. its value is the same as trc0. iic0 interrupt servicing main processing intiic0 flag setting data setting 368 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud the main processing of the slave operation is explained next. start serial interface iic0 and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. here, check the status by using the flags). the transmission operation is repeated until the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after that, the master issues a stop condition or restart condition. exit from the communication status occurs in this way. figure 18-22. slave operation flowchart (1/2) communication direction flag = 1? iic0 data iicc0 h iice0 = 1 data processing clear ready flag. wrel0 = 1 clear communication mode flag. wtim0 = 1 communication mode? ready? ackd0 = 1? no no no no communication mode? yes yes yes yes yes start no no no ready? data processing wrel0 = 1 acke0 = wtim0 = 1 clear ready flag. acke0 = 0 wrel0 = 1 read data. communication ends? communication mode? yes yes yes no 369 chapter 18 serial interface iic0 ( pd780078y subseries only) user s manual u14260ej3v1ud an example of the processing procedure of the slave with the intiic0 interrupt is explained below (processing is performed assuming that no extension code is used). the intiic0 interrupt checks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is checked and communication is completed if the address does not match. if the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the iic0 bus remaining in the wait status. remark <1> to <3> above correspond to <1> to <3> in figure 18-22 slave operation flowchart (2/2) . figure 18-22. slave operation flowchart (2/2) std0 = 1 clear communication mode flag. lrel0 = 1 end processing yes yes yes <2> <3> <1> spd0 = 1 no no generate intiic0 complete interrupt servicing. set ready flag complete interrupt servicing. coi0 = 1? communication direction flag trc0 set communication mode flag and clear ready flag. complete interrupt servicing. no chapter 18 serial interface iic0 ( pd780078y subseries only) 370 user? manual u14260ej3v1ud spt0 = 1 spt0 = 1 18.5.16 timing of i 2 c interrupt request (intiic0) occurrence the intiic0 interrupt request timing and the iic status register 0 (iics0) settings corresponding to that timing are described below. (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 1000 110b 2 : iics0 = 1000 000b 3 : iics0 = 1000 000b (sets wtim0) 4 : iics0 = 1000 00b (sets spt0) 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 100b 3 : iics0 = 1000 00b (sets spt0) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 371 user? manual u14260ej3v1ud stt0 = 1 spt0 = 1 stt0 = 1 spt0 = 1 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 7 1 : iics0 = 1000 110b 2 : iics0 = 1000 000b (sets wtim0) 3 : iics0 = 1000 00b (clears wtim0, sets stt0) 4 : iics0 = 1000 110b 5 : iics0 = 1000 000b (sets wtim0) 6 : iics0 = 1000 00b (sets spt0) 7 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 1000 110b 2 : iics0 = 1000 00b (sets stt0) 3 : iics0 = 1000 110b 4 : iics0 = 1000 00b (sets spt0) 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 372 user? manual u14260ej3v1ud spt0 = 1 spt0 = 1 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 1010 110b 2 : iics0 = 1010 000b 3 : iics0 = 1010 000b (sets wtim0) 4 : iics0 = 1010 00b (sets spt0) 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1010 110b 2 : iics0 = 1010 100b 3 : iics0 = 1010 00b (sets spt0) 4 : iics0 = 00001001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 373 user? manual u14260ej3v1ud (2) slave device operation (slave address data reception time (matches with sva0)) (a) start ~ address ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0001 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 100b 3 : iics0 = 0001 00b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 374 user? manual u14260ej3v1ud (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0001 110b 4 : iics0 = 0001 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0001 110b 2 : iics0 = 0001 00b 3 : iics0 = 0001 110b 4 : iics0 = 0001 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 375 user? manual u14260ej3v1ud (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 0010 010b 4 : iics0 = 0010 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 1 : iics0 = 0001 110b 2 : iics0 = 0001 00b 3 : iics0 = 0010 010b 4 : iics0 = 0010 110b 5 : iics0 = 0010 00b 6 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 376 user? manual u14260ej3v1ud (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 000b 3 : iics0 = 00000 10b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0001 110b 2 : iics0 = 0001 00b 3 : iics0 = 00000 10b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 377 user? manual u14260ej3v1ud (3) slave device operation (when receiving extension code) (a) start ~ code ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 0010 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 100b 4 : iics0 = 0010 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 378 user? manual u14260ej3v1ud (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 0001 110b 4 : iics0 = 0001 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 00b 4 : iics0 = 0001 110b 5 : iics0 = 0001 00b 6 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 379 user? manual u14260ej3v1ud (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 0010 010b 4 : iics0 = 0010 000b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 6 7 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 00b 4 : iics0 = 0010 010b 5 : iics0 = 0010 110b 6 : iics0 = 0010 00b 7 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 380 user? manual u14260ej3v1ud (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0010 010b 2 : iics0 = 0010 000b 3 : iics0 = 00000 10b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) st ad6-ad0 rw ak d7-d0 ak st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0010 010b 2 : iics0 = 0010 110b 3 : iics0 = 0010 00b 4 : iics0 = 00000 10b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 1 : iics0 = 00000001b remark : generated only when spie0 = 1 chapter 18 serial interface iic0 ( pd780078y subseries only) 381 user? manual u14260ej3v1ud (5) arbitration loss operation (operation as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0101 110b ( example when ald0 is read during interrupt servicing) 2 : iics0 = 0001 000b 3 : iics0 = 0001 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0101 110b ( example when ald0 is read during interrupt servicing) 2 : iics0 = 0001 100b 3 : iics0 = 0001 00b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 382 user? manual u14260ej3v1ud (b) when arbitration loss occurs during transmission of extension code (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) 2 : iics0 = 0010 000b 3 : iics0 = 0010 000b 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 4 5 1 : iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) 2 : iics0 = 0010 110b 3 : iics0 = 0010 100b 4 : iics0 = 0010 00b 5 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 383 user? manual u14260ej3v1ud (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data (when wtim0 = 1) st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 1 : iics0 = 01000110b ( example when ald0 is read during interrupt servicing) 2 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (b) when arbitration loss occurs during transmission of extension data st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 1 : iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) sets lrel0 = 1 by software 2 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care chapter 18 serial interface iic0 ( pd780078y subseries only) 384 user? manual u14260ej3v1ud (c) when arbitration loss occurs during transmission of data (i) when wtim0 = 0 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 1 : iics0 = 10001110b 2 : iics0 = 01000000b ( example when ald0 is read during interrupt servicing) 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (ii) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak sp 1 2 3 1 : iics0 = 10001110b 2 : iics0 = 01000100b ( example when ald0 is read during interrupt servicing) 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 chapter 18 serial interface iic0 ( pd780078y subseries only) 385 user? manual u14260ej3v1ud (d) when loss occurs due to restart condition during data transfer (i) not extension code (example: unmatches with sva0, wtim0 = 1) st ad6-ad0 rw ak d7-dn st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 01000110b ( example when ald0 is read during interrupt servicing) 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care n = 6 to 0 (ii) extension code st ad6-ad0 rw ak d7-dn st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) sets lrel0 = 1 by software 3 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care n = 6 to 0 chapter 18 serial interface iic0 ( pd780078y subseries only) 386 user? manual u14260ej3v1ud (e) when loss occurs due to stop condition during data transfer st ad6-ad0 rw ak d7-dn sp 1 2 1 : iics0 = 1000 110b 2 : iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don? care n = 6 to 0 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 100b (sets stt0) 3 : iics0 = 01000100b ( example when ald0 is read during interrupt servicing) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak sp 1 2 3 1 : iics0 = 1000 110b 2 : iics0 = 1000 00b (sets stt0) 3 : iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don? care stt0 = 1 stt0 = 1 chapter 18 serial interface iic0 ( pd780078y subseries only) 387 user? manual u14260ej3v1ud (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) when wtim0 = 1 st ad6-ad0 rw ak d7-d0 ak d7-d0 ak d7-d0 ak sp 1 2 3 4 1 : iics0 = 1000 110b 2 : iics0 = 1000 00b (sets spt0) 3 : iics0 = 01000000b ( example when ald0 is read during interrupt servicing) 4 : iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care spt0 = 1 chapter 18 serial interface iic0 ( pd780078y subseries only) 388 user? manual u14260ej3v1ud 18.6 timing charts when using the i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trc0 bit (bit 3 of iic status register 0 (iics0)), which specifies the data transfer direction, and then starts serial communication with the slave device. figures 18-23 and 18-24 show timing charts of the data communication. iic shift register 0 (iic0)? shift operation is synchronized with the falling edge of the serial clock (scl0). the transmit data is transferred to the so0 latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iic0 at the rising edge of scl0. chapter 18 serial interface iic0 ( pd780078y subseries only) 389 user? manual u14260ej3v1ud figure 18-23. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ~ address note to cancel slave wait, write ?fh?to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 a6 a5 a4 a3 a2 a1 a0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note chapter 18 serial interface iic0 ( pd780078y subseries only) 390 user s manual u14260ej3v1ud figure 18-23. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (2) data note to cancel slave wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh note iic0 ffh note iic0 data transmit receive note note chapter 18 serial interface iic0 ( pd780078y subseries only) 391 user s manual u14260ej3v1ud figure 18-23. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition note to cancel slave wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 a5 a6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) chapter 18 serial interface iic0 ( pd780078y subseries only) 392 user s manual u14260ej3v1ud figure 18-24. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ~ address note to cancel master wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l h h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 a6 a5 a4 a3 a2 a1 a0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition chapter 18 serial interface iic0 ( pd780078y subseries only) 393 user s manual u14260ej3v1ud figure 18-24. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (2) data note to cancel master wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note chapter 18 serial interface iic0 ( pd780078y subseries only) 394 user s manual u14260ej3v1ud figure 18-24. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition note to cancel master wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l h acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 a5 a6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) n ? ack (when spie0 = 1) 395 user? manual u14260ej3v1ud chapter 19 interrupt functions 19.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupts a non-maskable interrupt is acknowledged even when interrupts are disabled. it does not undergo priority control and is given top priority over all other interrupt requests. however, interrupt requests are held pending during non-maskable interrupt servicing. a non-maskable interrupt generates a standby release signal and releases the halt mode during main system clock operation. the only non-maskable interrupt in the pd780078 subseries is the interrupt from the watchdog timer. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). high priority interrupts can be serviced preferentially to low priority interrupts (multiple interrupt servicing). if two or more interrupts with the same priority are generated simultaneously, each interrupt has a predetermined priority (see table 19-1 ). a standby release signal is generated and the stop mode and halt mode are released. five external interrupt requests and 18 internal interrupt requests (19 internal interrupt requests for the pd780078y subseries) are incorporated as maskable interrupts. (3) software interrupts a software interrupt is a vectored interrupt that is generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. a software interrupt does not undergo interrupt priority control. 19.2 interrupt sources and configuration a total of 25 interrupt sources (26 interrupt sources for the pd780078y subseries) exist among non-maskable, maskable, and software interrupts (see table 19-1 ). remark a non-maskable interrupt or maskable interrupt (internal) can be selected as the watchdog timer interrupt source (intwdt). chapter 19 interrupt functions 396 user? manual u14260ej3v1ud table 19-1. interrupt source list (1/2) type of default interrupt source internal/ vector table interrupt priority note 1 name trigger external address non- intwdt watchdog timer overflow (non-maskable internal 0004h (a) maskable interrupt selected) maskable 0 intwdt watchdog timer overflow (interval timer (b) selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 generation of uart0 reception error internal 000eh (b) 6 intsr0 end of uart0 reception 0010h 7 intst0 end of uart0 transmission 0012h 8 intcsi1 end of csi1 communication 0014h 9 intcsi3 end of sio3 communication 0016h 10 intiic0 note 3 end of iic0 communication 0018h 11 intwti reference time interval signal from watch timer 001ah 12 inttm000 match of tm00 and cr000 001ch (when compare register is specified) detection of valid edge of ti010 (when capture register is specified) 13 inttm010 match of tm00 and cr010 001eh (when compare register is specified) detection of valid edge of ti000 (when capture register is specified) 14 inttm50 match of tm50 and cr50 0020h 15 inttm51 match of tm51 and cr51 0022h 16 intad0 end of conversion by a/d converter 0024h 17 intwt watch timer overflow 0026h 18 intkr falling edge detection of port 4 external 0028h (d) notes 1. the default priority is the priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest and 23 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 19-1. 3. pd780078y subseries only. basic configuration type note 2 chapter 19 interrupt functions 397 user? manual u14260ej3v1ud table 19-1. interrupt source list (2/2) type of default interrupt source internal/ vector table interrupt priority note 1 name trigger external address maskable 19 intser2 generation of uart2 reception error internal 002ah (b) 20 intsr2 end of uart2 reception 002ch 21 intst2 note 3 end of uart2 transmission note 4 /data transfer note 5 002eh 22 inttm001 match of tm01 and cr001 0030h (when compare register is specified) detection of valid edge of ti011 (when capture register is specified) 23 inttm011 match of tm01 and cr011 0032h (when compare register is specified) detection of valid edge of ti001 (when capture register is specified) software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest and 23 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 19-1. 3. interrupt sources can be selected by the transmit interrupt signal select flag (ismd2). 4. an interrupt request signal is generated when all the data in transmit buffer register 2 (txb2) has been transmitted. 5. an interrupt request signal is generated when data transfer is completed from txb2 to the transmit shift register (txs2). basic configuration type note 2 chapter 19 interrupt functions 398 user? manual u14260ej3v1ud figure 19-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus interrupt request priority controller vector table address generator standby release signal internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector chapter 19 interrupt functions 399 user s manual u14260ej3v1ud figure 19-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mem: memory expansion mode register if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal falling edge detector 1 when mem = 01h internal bus interrupt request vector table address generator chapter 19 interrupt functions 400 user s manual u14260ej3v1ud 19.3 interrupt function control registers the following 6 types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h, if1l) interrupt mask flag register (mk0l, mk0h, mk1l) priority specification flag register (pr0l, pr0h, pr1l) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) program status word (psw) table 19-2 gives a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 19-2. flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt wdtif note 1 if0l wdtmk note 1 mk0l wdtpr note 1 pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intser0 serif0 sermk0 serpr0 intsr0 srif0 srmk0 srpr0 intst0 stif0 stmk0 stpr0 intcsi1 csiif1 if0h csimk1 mk0h csipr1 pr0h intcsi3 csiif3 csimk3 csipr3 intiic0 note 2 iicif0 note 2 iicmk0 note 2 iicpr0 note 2 intwti wtiif0 wtimk0 wtipr0 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 intad0 adif0 if1l admk0 mk1l adpr0 pr1l intwt wtif wtmk wtpr intkr krif krmk krpr intser2 serif2 sermk2 serpr2 intsr2 srif2 srmk2 srpr2 intst2 stif2 stmk2 stpr2 inttm001 tmif001 tmmk001 tmpr001 inttm011 tmif011 tmmk011 tmpr011 notes 1. interrupt control flag when watchdog timer is used as interval timer 2. pd780078y subseries only chapter 19 interrupt functions 401 user s manual u14260ej3v1ud (1) interrupt request flag registers (if0l, if0h, if1l) an interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset input. when an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then the interrupt routine is executed. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are read by a 16-bit memory manipulation instruction. reset input clears if0l, if0h, and if1l to 00h. figure 19-2. format of interrupt request flag register (if0l, if0h, if1l) address: ffe0h after reset: 00h r/w symbol 76543210 if0l stif0 srif0 serif0 pif3 pif2 pif1 pif0 wdtif address: ffe1h after reset: 00h r/w symbol 76543210 if0h tmif51 tmif50 tmif010 tmif000 wtiif0 iicif0 note csiif3 csiif1 address: ffe2h after reset: 00h r/w symbol 76543210 if1l tmif011 tmif001 stif2 srif2 serif2 krif wtif adif0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request signal is generated, interrupt request status note incorporated only in the pd780078y subseries. be sure to set 0 for the pd780078 subseries. cautions 1. the wdtif flag is r/w enabled only when the watchdog timer is used as an interval timer. if watchdog timer mode 1 is used, set the wdtif flag to 0. 2. when operating a timer, serial interface, or a/d converter after standby release, operate it after clearing the interrupt request flag, because interrupt request flags may be set by noise. 3. when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr1). when describing in c language, use a bit manipulation instruction such as ?f0l.0 = 0;?or ?asm(?lr1 if0l, 0?;?because the compiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?f0l &= 0xfe;?and compiled, it becomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?ov a, if0l?and ?ov if0l, a? the flag is cleared to 0 at ?ov if0l, a? therefore, care must be exercised when using an 8-bit memory manipulation instruction in c language. chapter 19 interrupt functions 402 user s manual u14260ej3v1ud (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form 16-bit register mk0, they are set by a 16-bit memory manipulation instruction. reset input sets mk0l, mk0h, and mk1l to ffh. figure 19-3. format of interrupt mask flag register (mk0l, mk0h, mk1l) address: ffe4h after reset: ffh r/w symbol 76543210 mk0l stmk0 srmk0 sermk0 pmk3 pmk2 pmk1 pmk0 wdtmk address: ffe5h after reset: ffh r/w symbol 76543210 mk0h tmmk51 tmmk50 tmmk010 tmmk000 wtimk0 iicmk0 note csimk3 csimk1 address: ffe6h after reset: ffh r/w symbol 76543210 mk1l tmmk011 tmmk001 stmk2 srmk2 sermk2 krmk wtmk admk0 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note incorporated only in the pd780078y subseries. be sure to set 1 for the pd780078 subseries. cautions 1. if the watchdog timer is used in watchdog timer mode 1, the contents of the wdtmk flag become undefined when read. 2. because port 0 pins have an alternate function as external interrupt request inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. chapter 19 interrupt functions 403 user s manual u14260ej3v1ud (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flag registers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are set by a 16-bit memory manipulation instruction. reset input sets pr0l, pr0h, and pr1l to ffh. figure 19-4. format of priority specification flag register (pr0l, pr0h, pr1l) address: ffe8h after reset: ffh r/w symbol 76543210 pr0l stpr0 srpr0 serpr0 ppr3 ppr2 ppr1 ppr0 wdtpr address: ffe9h after reset: ffh r/w symbol 76543210 pr0h tmpr51 tmpr50 tmpr010 tmpr000 wtipr0 iicpr0 note csipr3 csipr1 address: ffeah after reset: ffh r/w symbol 76543210 pr1l tmpr011 tmpr001 stpr2 srpr2 serpr2 krpr wtpr adpr0 xxprx priority level selection 0 high priority level 1 low priority level note incorporated only in the pd780078y subseries. be sure to set 1 for the pd780078 subseries. caution when the watchdog timer is used in watchdog timer mode 1, set the wdtpr flag to 1. chapter 19 interrupt functions 404 user s manual u14260ej3v1ud (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears egp and egn to 00h. figure 19-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 76543210 egp 0000 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 76543210 egn 0000 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 19-3 shows the ports corresponding to egpn and egnn. table 19-3. ports corresponding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p00 intp0 egp1 egn1 p01 intp1 egp2 egn2 p02 intp2 egp3 egn3 p03 intp3 caution when the function is switched from external interrupt request to port, edge detection may be performed. therefore, clear egpn and egnn to 0 before switching to the port mode. remark n = 0 to 3 chapter 19 interrupt functions 405 user s manual u14260ej3v1ud (5) program status word (psw) the program status word is a register used to hold the instruction execution results and the current status for an interrupt request. an ie flag to set maskable interrupt enable/disable and an isp flag to control nesting processing are mapped to the psw. besides 8-bit read/write, this register can be operated by bit manipulation and dedicated (ei and di) instructions. when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-6. format of program status word 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupts disabled) ie 0 1 disable priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enable interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 chapter 19 interrupt functions 406 user s manual u14260ej3v1ud 19.4 interrupt servicing operations 19.4.1 non-maskable interrupt request acknowledgment operation a non-maskable interrupt request is unconditionally acknowledged even in an interrupt acknowledgment disabled state. it does not undergo interrupt priority control and has the highest priority of all interrupts. if a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag and isp flag are reset (0), and the contents of the vector table are loaded into the pc and branched. this disables the acknowledgment of multiple interrupts. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction has been executed. however, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program. figures 19-7, 19-8, and 19-9 show the flowchart of non-maskable interrupt request generation through acknowledgment, the acknowledgment timing of a non-maskable interrupt request, and the acknowledgment operation when multiple non-maskable interrupt requests are generated, respectively. caution be sure to use the reti instruction to restore processing from the non-maskable interrupt. chapter 19 interrupt functions 407 user s manual u14260ej3v1ud figure 19-7. flowchart of non-maskable interrupt request generation to acknowledgment figure 19-8. non-maskable interrupt request acknowledgment timing start wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdt interrupt servicing? interrupt control register not accessed? interval timer no reset processing no interrupt request generation start of interrupt servicing interrupt request held pending no no no yes yes yes yes yes wdtm: watchdog timer mode register wdt: watchdog timer wdtm3 = 0 (with non-maskable interrupt selected)? instruction instruction psw, pc save, jump to interrupt servicing interrupt service program cpu processing wdtif interrupt request generated during this interval is acknowledged at . wdtif: watchdog timer interrupt request flag chapter 19 interrupt functions 408 user s manual u14260ej3v1ud figure 19-9. non-maskable interrupt request acknowledgment operation (a) if a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction nmi request <2> execution of nmi request <1> nmi request <2> held pending servicing of pending nmi request <2> main routine nmi request <1> execution of 1 instruction execution of nmi request <1> nmi request <2> held pending nmi request <3> held pending servicing of pending nmi request <2> nmi request <3> not acknowledged (although two or more nmi requests have been generated, only one request is acknowledged.) nmi request <2> nmi request <3> chapter 19 interrupt functions 409 user s manual u14260ej3v1ud 19.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are enabled (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). moreover, even if the ei instruction is executed during execution of a non-maskable interrupt servicing program, neither non-maskable interrupt requests nor maskable interrupt requests are acknowledged. the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 19-4 below. for the interrupt request acknowledgment timing, see figures 19-11 and 19-12 . table 19-4. times from generation of maskable interrupt request until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified by the priority specification flag is acknowledged first. if two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 19-10 shows the interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into the pc and branched. return from an interrupt is possible using the reti instruction. chapter 19 interrupt functions 410 user s manual u14260ej3v1ud figure 19-10. interrupt request acknowledgment processing algorithm if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgment of maskable interrupt requests (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request received, or low-priority interrupt servicing) start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any interrupt request among those simultaneously generated with pr = 0? chapter 19 interrupt functions 411 user s manual u14260ej3v1ud figure 19-11. interrupt request acknowledgment timing (minimum time) remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 19-12. interrupt request acknowledgment timing (maximum time) remark 1 clock: 1/f cpu (f cpu : cpu clock) 19.4.3 software interrupt request acknowledgment operation a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into the pc and branched. return from a software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from a software interrupt. 8 clocks 7 clocks instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 33 clocks 32 clocks instruction divide instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks chapter 19 interrupt functions 412 user? manual u14260ej3v1ud 19.4.4 multiple interrupt servicing multiple interrupt servicing occurs when an interrupt request is acknowledged during execution of another interrupt. multiple interrupt servicing does not occur unless the interrupt request acknowledgment enable state is selected (ie = 1) (except non-maskable interrupts). when an interrupt request is received, interrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. interrupt requests that are not enabled because of the interrupt disabled state or they have a lower priority are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction. multiple interrupt servicing is not possible during non-maskable interrupt servicing. table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 19- 13 shows multiple interrupt servicing examples. table 19-5. relationship between interrupt requests enabled for multiple interrupt servicing multiple interrupt non-maskable maskable interrupt request software request interrupt request pr = 0 pr = 1 interrupt interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 request non-maskable interrupt maskable interrupt isp = 0 isp = 1 software interrupt remarks 1. : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0: higher priority level pr = 1: lower priority level chapter 19 interrupt functions 413 user s manual u14260ej3v1ud figure 19-13. examples of multiple interrupt servicing (1/2) example 1. multiple interrupt servicing occurs twice during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. nesting does not occur due to priority control interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 1 ie = 1 ie = 1 ie = 0 ie = 0 main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 1 ie = 1 ie = 0 ei 1 instruction execution reti chapter 19 interrupt functions 414 user s manual u14260ej3v1ud figure 19-13. examples of multiple interrupt servicing (2/2) example 3. multiple interrupt servicing does not occur because interrupts are not enabled interrupts are not enabled during servicing of interrupt intxx (ei instruction is not issued), so interrupt request intyy is not acknowledged and multiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 1 ie = 1 ie = 0 chapter 19 interrupt functions 415 user s manual u14260ej3v1ud 19.4.5 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. mov psw, #byte mov a, psw mov psw, a mov1 psw. bit, cy mov1 cy, psw. bit and1 cy, psw. bit or1 cy, psw. bit xor1 cy, psw. bit set1 psw. bit clr1 psw. bit retb reti push psw pop psw bt psw. bit, $addr16 bf psw. bit, $addr16 btclr psw. bit, $addr16 ei di manipulation instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, and pr1l registers caution the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared to 0. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. however, a non-maskable interrupt request is acknowledged. figure 19-14 shows the timing at which interrupt requests are held pending. figure 19-14. interrupt request hold remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program cpu processing if 416 user? manual u14260ej3v1ud chapter 20 external device expansion function use the expanded-specification products of the pd780076, 780078, and 78f0078, under the conventional- specification conditions (f x = 8.38 mhz: v dd = 4.0 to 5.5 v, f x = 5 mhz: v dd = 2.7 to 5.5 v, f x = 1.25 mhz: v dd = 1.8 to 5.5 v). the external device expansion function cannot be used under the expanded-specification conditions (high-speed operation). 20.1 external device expansion function the external device expansion function connects external devices to areas other than the internal rom, ram, and sfr. connection of external devices uses ports 4 to 6. ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc. table 20-1. pin functions in external memory expansion mode pin function when external device is connected alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 20-2. state of port 4 to 6 pins in external memory expansion mode caution when the external wait function is not used, the wait pin can be used as a port in all modes. port port 4 port 5 port 6 external expansion mode 0 to 7 0 1 2 3 4 5 6 7 4 5 6 7 single-chip mode port port port 256-byte expansion mode address/data port rd, wr, wait, astb 4 kb expansion mode address/data address port rd, wr, wait, astb 16 kb expansion mode address/data address port rd, wr, wait, astb full-address mode address/data address rd, wr, wait, astb chapter 20 external device expansion function 417 user? manual u14260ej3v1ud the memory maps when the external device expansion function is used are as follows. figure 20-1. memory map when using external device expansion function (a) memory map of pd780076, 780076y, and of pd78f0078, 78f0078y when flash memory size is 48 kb (b) memory map of pd780078, 780078y and of pd78f0078, 78f0078y when flash memory size is 60 kb sfr internal high-speed ram internal expansion ram full-address mode (when mm2 to mm0 = 111) or 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh ff00h feffh fb00h faffh f400h f3ffh d000h cfffh c100h c0ffh c000h bfffh 0000h ffffh ff00h feffh fb00h faffh f400h f3ffh f100h f0ffh f000h efffh 0000h sfr internal high-speed ram internal expansion ram full-address mode (when mm2 to mm0 = 111) or 16 kb expansion mode (when mm2 to mm0 = 101) or 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode f800h f7ffh f800h f7ffh reserved reserved chapter 20 external device expansion function 418 user s manual u14260ej3v1ud 20.2 external device expansion function control registers the external device expansion function is controlled by the following two registers. memory expansion mode register (mem) memory expansion wait setting register (mm) (1) memory expansion mode register (mem) mem sets the external expansion area. mem is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears mem to 00h. figure 20-2. format of memory expansion mode register (mem) address: ff47h after reset: 00h r/w symbol 76543210 mem 00000mm2mm1mm0 mm2 mm1 mm0 single-chip/memory p40 to p47, p50 to p57, p64 to p67 pin state expansion mode selection p40 to p47 p50 to p53 p54, p55 p56, p57 p64 to p67 0 0 0 single-chip mode port mode 0 0 1 port 4 falling edge detection mode 0 1 1 memory 256-byte ad0 to ad7 port mode p64 = rd expansion mode p65 = wr 100 mode note 4 kb a8 to a11 port mode p66 =wait mode p67 = astb 1 0 1 16 kb a12, a13 port mode mode 111 full-address a14, a15 mode other than above setting prohibited caution when using the falling edge detection function of port 4, be sure to set mem to 01h. (note is shown in the next page.) chapter 20 external device expansion function 419 user s manual u14260ej3v1ud note when the cpu accesses the external memory expansion area, the lower bits of the address to be accessed are output to the specified pins (except in the full-address mode). figure 20-3. pins specified for address (with pd780076 and 780076y) external expansion mode address accessed pins specified for address by cpu a15 a14 a13 a12 a11 a10 a9 a8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 256-byte expansion mode c000h (1) (1) (0) (0) (0) (0) (0) (0) 00000000 c001h (1) (1) (0) (0) (0) (0) (0) (0) 00000001 c055h (1) (1) (0) (0) (0) (0) (0) (0) 01010101 c0feh (1) (1) (0) (0) (0) (0) (0) (0) 11111110 c0ffh (1) (1) (0) (0) (0) (0) (0) (0) 11111111 4 kb expansion mode c000h (1) (1) (0) (0) 000000000000 c001h (1) (1) (0) (0) 000000000001 c100h (1) (1) (0) (0) 000100000000 cfffh (1) (1) (0) (0) 111111111111 16 kb expansion mode c000h (1) (1) 00000000000000 d000h (1) (1) 01000000000000 e000h (1) (1) 10000000000000 f000h (1) (1) 11000000000000 f3ffh (1) (1) 11001111111111 full-address mode c000h 1100000000000000 c001h 1100000000000001 f3ffh 1111001111111111 remark the value in ( ) is not actually output. this pin can be used as a port pin. (2) memory expansion wait setting register (mm) mm sets the number of waits. mm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 20-4. format of memory expansion wait setting register (mm) address: fff8h after reset: 10h r/w symbol 76543210 mm 00pw1pw00000 pw1 pw0 wait control 0 0 no wait 0 1 wait (one wait state inserted) 1 0 setting prohibited 1 1 wait control by external wait pin cautions 1. to control wait by the external wait pin, be sure to set the wait/p66 pin to input mode (set bit 6 (pm66) of port mode register 6 (pm6) to 1). 2. when wait is not controlled by the external wait pin, the wait/p66 pin can be used as an i/o port pin. chapter 20 external device expansion function 420 user s manual u14260ej3v1ud 20.3 external device expansion function timing the timing control signal output pins in the external memory expansion mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is output when data is read and instructions are fetched from external memory. during internal memory read, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output when data is written to external memory. during internal memory write, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an i/o port pin. during internal memory access, the external wait signal is ignored. (4) astb pin (alternate function: p67) address strobe signal output pin. the address strobe signal is output regardless of data access and instruction fetch from external memory. during internal memory access, the address strobe signal is output. (5) ad0 to ad7, a8 to a15 pins (alternate function: p40 to p47, p50 to p57) address/data signal output pins. a valid signal is output or input during data accesses and instruction fetches from external memory. these signals change even during internal memory access (output values are undefined). the timing charts are shown in figures 20-5 to 20-8. chapter 20 external device expansion function 421 user s manual u14260ej3v1ud figure 20-5. instruction fetch from external memory (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 lower address instruction code higher address rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address instruction code higher address rd astb ad0 to ad7 a8 to a15 wait lower address instruction code higher address chapter 20 external device expansion function 422 user s manual u14260ej3v1ud figure 20-6. external memory read timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 lower address read data higher address rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address read data higher address rd astb ad0 to ad7 a8 to a15 wait lower address read data higher address chapter 20 external device expansion function 423 user s manual u14260ej3v1ud figure 20-7. external memory write timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting wr astb ad0 to ad7 a8 to a15 lower address write data higher address hi-z wr astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address write data higher address hi-z wr astb ad0 to ad7 a8 to a15 wait lower address write data higher address hi-z chapter 20 external device expansion function 424 user s manual u14260ej3v1ud figure 20-8. external memory read-modify-write timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting remark the read-modify-write timing is the operation when a bit manipulation instruction is executed. read data write data higher address hi-z lower address rd astb ad0 to ad7 a8 to a15 wr rd astb ad0 to ad7 a8 to a15 hi-z wr write data higher address internal wait signal (1-clock wait) read data lower address wait hi-z rd astb ad0 to ad7 a8 to a15 wr write data higher address read data lower address chapter 20 external device expansion function 425 user s manual u14260ej3v1ud 20.4 example of connection with memory this section provides an example of connecting the pd780078 with the external memory (sram) in figure 20- 9. in addition, the external device expansion function is used in the full-address mode, the addresses from 0000h to efffh (60 kb) are allocated to internal rom, and the addresses after f000h are allocated to sram. figure 20-9. connection example of pd780078 and memory rd wr a8 to a14 astb ad0 to ad7 v dd0 74hc573 le d0 to d7 oe q0 to q7 pd43256b cs oe we i/o1 to i/o8 a0 to a14 data bus pd780078 address bus 426 user? manual u14260ej3v1ud chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode stops the cpu operation clock. if the main system clock oscillator or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, power consumption is not decreased as much as in the stop mode. however, the halt mode is effective to restart operation immediately upon an interrupt request and to carry out intermittent operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu power consumption. data memory low-voltage hold (down to v dd = 1.6 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low power consumption. because this mode can be released upon an interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to stabilize oscillation after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon an interrupt request. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when operation is transferred to the stop mode, be sure to stop operation of the peripheral hardware operating with the main system clock before executing the stop instruction. 3. the following sequence is recommended for reducing the power consumption of the a/d converter when the standby function is used: first clear bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. chapter 21 standby function 427 user? manual u14260ej3v1ud 21.1.2 standby function control register the wait time after the stop mode is released upon an interrupt request is controlled by the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. therefore, when the stop mode is released by inputting reset, it takes 2 17 / f x until release. remark for the registers that start, stop, or select the clock, see chapter 7 clock generator . figure 21-1. format of oscillation stabilization time select register (osts) address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time f x = 8.38 mhz f x = 12 mhz note 0002 12 /f x 488 s 341 s 0012 14 /f x 1.95 ms 1.36 ms 0102 15 /f x 3.91 ms 2.73 ms 0112 16 /f x 7.82 ms 5.46 ms 1002 17 /f x 15.6 ms 10.9 ms other than above setting prohibited note expanded-specification products of pd780078 subseries only. caution the wait time after the stop mode is released does not include the time (see ??in the illustration below) from stop mode release to clock oscillation start. this applies regardless of whether stop mode is released by reset input or by interrupt request generation. stop mode release x1 pin voltage waveform a remark f x : main system clock oscillation frequency chapter 21 standby function 428 user s manual u14260ej3v1ud 21.2 standby function operations 21.2.1 halt mode (1) halt mode setting and operating statuses the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating statuses in the halt mode are described below. table 21-1. halt mode operating statuses halt mode halt instruction execution when halt instruction execution when setting using main system clock using subsystem clock without subsystem with subsystem with main system with main system item clock note 1 clock note 2 clock oscillation clock oscillation stopped clock generator both main system clock and subsystem clock can be oscillated. clock supply to cpu stops. cpu operation stops. ports (output latches) status before halt mode setting is held. 16-bit timer/event operable stop counters 00, 01 8-bit timer/event operable operable when ti50, counters 50, 51 ti51 are selected as count clock. watch timer operable when f x /2 7 is operable operable when f xt is selected as count clock selected as count clock. watchdog timer operable operation stops. clock output operable when f x to f x /2 7 is operable operable when f xt is selected as output clock selected as output clock. buzzer output operable buz is at low level. a/d converter stop serial interface operable operable during external clock input. external interrupt operable bus line ad0 to ad7 high impedance during a8 to a15 status before halt mode setting is held. external astb low level expansion wr, rd high level wait high impedance notes 1. including case when external clock is not supplied. 2. including case when external clock is supplied. chapter 21 standby function 429 user s manual u14260ej3v1ud (2) halt mode release the halt mode can be released by the following three sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the instruction at the next address is executed. figure 21-2. halt mode release by interrupt request generation remarks 1. the broken lines indicate the case when the interrupt request that released the standby mode is acknowledged. 2. the wait times are as follows: when vectored interrupt servicing is carried out: 8 or 9 clocks when vectored interrupt servicing is not carried out: 2 or 3 clocks (b) release by non-maskable interrupt request when a non-maskable interrupt request is generated, the halt mode is released and vectored interrupt servicing is carried out whether interrupt acknowledgment is enabled or disabled. however, a non-maskable interrupt request is not generated during operation with the subsystem clock. halt instruction wait wait operation mode halt mode operation mode oscillation clock standby release signal interrupt request cpu status chapter 21 standby function 430 user s manual u14260ej3v1ud (c) release by reset input when the reset signal is input, halt mode is released. and, as in the case with normal reset operation, the program is executed after branch to the reset vector address. figure 21-3. halt mode release by reset input remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 21-2. operation in response to interrupt request in halt mode release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt servicing execution 0101 next address instruction execution 01 0 0111 interrupt servicing execution 1 halt mode hold non-maskable interrupt request interrupt servicing execution reset input reset processing : don t care halt instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode halt mode operating mode oscillation stop clock reset signal oscillation oscillation reset period cpu status chapter 21 standby function 431 user s manual u14260ej3v1ud 21.2.2 stop mode (1) stop mode setting and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. the operating mode is set after the wait set using the oscillation stabilization time select register (osts). the operating statuses in the stop mode are described in table 21-3 below. table 21-3. stop mode operating statuses stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock oscillation is stopped. cpu operation stops. ports (output latches) status before stop mode setting is held. 16-bit timer/event counters 00, 01 operation stops. 8-bit timer/event counters 50, 51 operable only when ti50, ti51 are selected as count clock. watch timer operable when f xt is selected as operation stops. count clock. watchdog timer operation stops. clock output operable when f xt is selected as pcl is at low level. output clock. buzzer output buz is at low level. a/d converter operation stops. serial interface other than uart0, 2 operable only when externally supplied clock is specified as the serial clock. uart0, 2 operation stops. (transmit shift register 0, 2 (txs0, txs2), receive shift register 0, 2 (rx0, rx2), receive buffer register 0, 2 (rxb0, rxb2) and transmit buffer register 2 (txb2) hold the value just before the clock stopped.) external interrupt operable bus line during ad0 to ad7 high impedance external expansion a8 to a15 status before stop mode setting is held. astb low level wr, rd high level wait high impedance chapter 21 standby function 432 user s manual u14260ej3v1ud (2) stop mode release the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. if interrupt acknowledgment is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledgment is disabled, the instruction at the next address is executed. figure 21-4. stop mode release by interrupt request generation remark the broken lines indicate the case when the interrupt request that released the standby status is acknowledged. stop instruction wait (time set by osts) oscillation stabilization wait status operating mode stop mode operating mode oscillation clock standby release signal oscillation stop oscillation interrupt request cpu status chapter 21 standby function 433 user s manual u14260ej3v1ud (b) release by reset input the stop mode is released when the reset signal is input, and the reset operation is carried out after the lapse of oscillation stabilization time. figure 21-5. stop mode release by reset input remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 21-4. operation in response to interrupt request in stop mode release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt servicing execution 0101 next address instruction execution 01 0 0111 interrupt servicing execution 1 stop mode hold reset input reset processing : don t care stop instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode stop mode operating mode oscillation stop clock reset signal oscillation oscillation reset period cpu status 434 user? manual u14260ej3v1ud chapter 22 reset function 22.1 reset function the following two operations are available to generate the reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 22-1. each pin is high impedance during reset input or during the oscillation stabilization time just after reset release. when a high level is input to the reset pin, the reset is released and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically released after the reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figures 22-2 to 22-4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is released by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 22-1. reset function block diagram reset count clock reset controller watchdog timer stop overflow reset signal interrupt function chapter 22 reset function 435 user s manual u14260ej3v1ud figure 22-2. timing of reset by reset input figure 22-3. timing of reset due to watchdog timer overflow figure 22-4. timing of reset in stop mode by reset input delay delay hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 watchdog timer overflow internal reset signal port pin delay delay hi-z normal operation oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop) chapter 22 reset function 436 user s manual u14260ej3v1ud table 22-1. hardware statuses after reset acknowledgment (1/2) hardware status after reset acknowledgment note 1 program counter (pc) contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose registers undefined note 2 port registers 0 to 8 (p0 to p8) (output latches) 00h (undefined only for p1) port mode registers 0, 2 to 8 (pm0, pm2 to pm8) ffh pull-up resistor option registers 0, 2 to 8 (pu0, pu2 to pu8) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh note 3 internal expansion ram size switching register (ixs) 0ch note 4 memory expansion mode register (mem) 00h memory expansion wait setting register (mm) 10h oscillation stabilization time select register (osts) 04h 16-bit timer/event counters timer counters 00, 01 (tm00, tm01) 0000h 00, 01 capture/compare registers 000, 001, 010, 011 undefined (cr000, cr001, cr010, cr011) prescaler mode registers 00, 01 (prm00, prm01) 00h capture/compare control registers 00, 01 (crc00, crc01) 00h mode control registers 00, 01 (tmc00, tmc01) 00h output control registers 00, 01 (toc00, toc01) 00h 8-bit timer/event counters timer counters 50, 51 (tm50, tm51) 00h 50, 51 compare registers 50, 51 (cr50, cr51) undefined clock select registers 50, 51 (tcl50, tcl51) 00h mode control registers 50, 51 (tmc50, tmc51) 00h watch timer operation mode register (wtm) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. although the initial value is cfh, set the following value for each version. pd780076, 780076y: cch pd780078, 780078y: cfh pd78f0078, 78f0078y: value for mask rom versions 4. although the default value of this register is 0ch, initialize this register to 0ah. chapter 22 reset function 437 user s manual u14260ej3v1ud table 22-1. hardware statuses after reset acknowledgment (2/2) hardware status after reset acknowledgment clock output/buzzer output controller clock output select register (cks) 00h a/d converter conversion result register 0 (adcr0) 0000h mode register 0 (adm0) 00h analog input channel specification register 0 (ads0) 00h serial interface uart0 asynchronous serial interface mode register 0 (asim0) 00h asynchronous serial interface status register 0 (asis0) 00h baud rate generator control register 0 (brgc0) 00h transmit shift register 0 (txs0) ffh receive buffer register 0 (rxb0) serial interface uart2 asynchronous serial interface mode register 2 (asim2) 00h transfer mode specification register 2 (trmc2) 02h clock select register 2 (cksel2) 00h baud rate generator control register 2 (brgc2) 00h asynchronous serial interface status register 2 (asis2) 00h asynchronous serial interface transmit status register 2 (asif2) 00h transmit buffer register 2 (txb2) ffh receive buffer register 2 (rxb2) ffh serial interface sio3 shift register 3 (sio3) undefined operation mode register 3 (csim3) 00h serial interface csi1 transmit buffer register 1 (sotb1) undefined shift register 1(sio1) undefined operation mode register 1 (csim1) 00h clock select register 1 (csic1) 10h serial interface iic0 note transfer clock select register 0 (iiccl0) 00h shift register 0 (iic0) 00h control register 0 (iicc0) 00h status register 0 (iics0) 00h slave address register 0 (sva0) 00h interrupt request flag registers (if0l, if0h, if1l) 00h mask flag registers (mk0l, mk0h, mk1l) ffh priority specification flag registers (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h note provided only in the pd780078y subseries. 438 user? manual u14260ej3v1ud chapter 23 pd78f0078, 78f0078y the pd78f0078 and 78f0078y are provided as the flash memory versions of the pd780078, 780078y subseries. the pd78f0078 and 78f0078y are products that incorporate flash memory in which the program can be written, erased, and rewritten while it is mounted on the board. writing to flash memory can be performed with the memory mounted on the target system (on board). a dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development environment and the applications using flash memory. software can be altered after the pd78f0078 and 78f0078y are solder-mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier. table 23-1 shows the differences between the pd78f0078 and 78f0078y and the mask rom versions. table 23-1. differences between pd78f0078 and mask rom versions item pd78f0078 pd780076 pd780078 internal rom configuration flash memory mask rom internal rom capacity 60 kb note 1 48 kb 60 kb mask option to specify on-chip not possible possible pull-up resistors of pins p30 to p33 note 2 ic pin none available v pp pin available none electrical specifications, refer to the chapters of electrical specifications and recommended soldering recommended soldering conditions conditions. notes 1. the same capacity as the mask rom versions can be specified by means of the memory size switching register (ims). 2. the p30 and p31 pins are provided only in the pd780078y subseries. caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions. chapter 23 pd78f0078, 78f0078y 439 user? manual u14260ej3v1ud 23.1 memory size switching register the pd78f0078 and 78f0078y allow users to select the internal memory capacity using the memory size switching register (ims) so that the same memory map as that of mask rom versions with a different internal memory capacity can be achieved. ims is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. caution be sure to set the values of the target mask rom version as the initial setting of the program. reset input initializes ims to cfh. also be sure to set the values of the target mask rom version after reset. figure 23-1. format of memory size switching register (ims) address: fff0h after reset: cfh r/w symbol 76543210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 110048 kb 111160 kb other than above setting prohibited the ims settings to obtain the same memory map as mask rom versions are shown in table 23-2. table 23-2. memory size switching register settings target mask rom versions ims setting pd780076, 780076y cch pd780078, 780078y cfh caution when using the mask rom versions, be sure to set ims to the value indicated in table 23-2. chapter 23 pd78f0078, 78f0078y 440 user? manual u14260ej3v1ud 23.2 internal expansion ram size switching register the internal expansion ram size switching register (ixs) is used to set the internal expansion ram capacity. ixs is set by an 8-bit memory manipulation instruction. reset input sets ixs to 0ch. caution be sure to set ixs to 0ah as the initial setting of the program. reset input initializes ixs to 0ch, so be sure to set ixs to 0ah after reset. set the mask rom versions in the same manner. figure 23-2. format of internal expansion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol 76543210 ixs 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixram4 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 01010 1024 bytes other than above setting prohibited chapter 23 pd78f0078, 78f0078y 441 user? manual u14260ej3v1ud 23.3 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the flash memory mounted on the target system (on-board). a flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. software can be modified after the microcontroller is solder-mounted on the target system. distinguishing software facilities low-quantity, varied model production easy data adjustment when starting mass production 23.3.1 programming environment the following shows the environment required for pd78f0078, 78f0078y flash memory programming. when flashpro iii or flashpro iv is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals of flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 23-3. environment for writing program to flash memory note iic is supported by the pd78f0078y only. rs-232c usb dedicated flash programmer pd78f0078, pd78f0078y v pp v dd v ss reset sio/uart/iic note host machine pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx y yyy statve chapter 23 pd78f0078, 78f0078y 442 user s manual u14260ej3v1ud 23.3.2 communication mode use the communication mode shown in table 23-3 to perform communication between the dedicated flash programmer and the pd78f0078, 78f0078y. table 23-3. communication mode list communication standard (type) setting note 1 pins used number of mode port speed on target frequency multiply v pp pulses (comm port) (sio clock) (cpu clock) (flashpro clock) rate (multiple rate) 3-wire serial i/o sio-ch1 2.4 khz to 625 khz note 2 optional 1 to 10 mhz note 2 1.0 si3/p34 1 (sio3) (sio ch-1) (100 hz to 1.25 mhz) note 2 so3/p35 sck3/p36 3-wire serial i/o sio-h/s si3/p34 3 (sio3) (sio ch-3 + so3/p35 with handshake handshake) sck3/p36 p31 (hs) i 2 c bus note 3 iic-ch0 10 k to 100 k baud note 2 optional 1 to 10 mhz note 2 1.0 sda0/p32 4 (iic0) (iic ch-0) (50 khz) scl0/p33 uart uart-ch0 4800 to 76800 baud notes 2, 4 optional 1 to 10 mhz note 2 1.0 r x d0/p23 8 (uart0) (uart ch-0) (4800 to 76800 bps) notes 2, 4 t x d0/p24 notes 1. selection items for standard settings on flashpro iv (type settings on flashpro iii). 2. the possible setting range differs depending on the voltage. for details, refer to chapters 25 to 27. 3. pd78f0078y only 4. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. remark items enclosed in parentheses in the setting item column are the set value and set item of flashpro iii when they differ from those of flashpro iv. figure 23-4. communication mode selection format 10 v v pp v pp pulse flash memory write mode reset v dd v ss v dd v ss chapter 23 pd78f0078, 78f0078y 443 user s manual u14260ej3v1ud figure 23-5. example of connection with dedicated flash programmer (1/2) (a) 3-wire serial i/o (sio3) dedicated flash programmer v pp v dd /reset sck so/txd si/rxd clk gnd v pp v dd0 note 1 , v dd1 note 1 , av ref reset sck3 si3 so3 x1 note 2 v ss0 , v ss1 , av ss pd78f0078, 78f0078y (b) 3-wire serial i/o (sio3) with handshake v pp v dd /reset sck so/txd si/rxd h/s gnd v pp v dd0 note 1 , v dd1 note 1 , av ref reset sck3 si3 so3 p31 (hs) clk x1 note 2 v ss0 , v ss1 , av ss pd78f0078, 78f0078y dedicated flash programmer (c) uart (uart0) v pp v dd /reset so/t x d si/r x d clk gnd v pp v dd0 note 1 , v dd1 note 1 , av ref reset r x d0 t x d0 x1 note 2 v ss0 , v ss1 , av ss pd78f0078, 78f0078y dedicated flash programmer notes 1. even if power is supplied on board, the v dd0 and v dd1 pins must be connected to v dd of the dedicated flash programmer. supply the v dd voltage before programming is started. 2. the x1 pin can be supplied on board. in this case, the pin does not need to be connected to the dedicated flash programmer. chapter 23 pd78f0078, 78f0078y 444 user s manual u14260ej3v1ud figure 23-5. example of connection with dedicated flash programmer (2/2) (d) i 2 c bus (iic0) v pp v dd /reset sck si/rxd clk gnd v pp v dd0 note 1 , v dd1 note 1 , av ref reset scl0 sda0 x1 note 2 v ss0 , v ss1 , av ss pd78f0078, 78f0078y dedicated flash programmer notes 1. even if power is supplied on board, the v dd0 and v dd1 pins must be connected to v dd of the dedicated flash programmer. supply the v dd voltage before programming is started. 2. the x1 pin can be supplied on board. in this case, the pin does not need to be connected to the dedicated flash programmer. if flashpro iii/flashpro iv is used as the dedicated flash programmer, the following signals are generated for the pd78f0078, 78f0078y. for details, refer to the manual of flashpro iii/flashpro iv. table 23-4. pin connection list signal name i/o pin function pin name sio3 sio3 (hs) uart0 iic0 note 1 v pp output write voltage v pp v dd i/o v dd voltage generation/voltage v dd0 , v dd1 , av ref note 2 note 2 note 2 note 2 monitoring gnd ground v ss0 , v ss1 , av ss clk output clock output x1 /reset output reset signal reset si/r x d input reception signal so3/txd0/sda0 note 1 so/t x d output transmission signal si3/rxd0 sck output transfer clock sck3/scl0 note 1 h/s input handshake signal p31 (hs) notes 1. pd78f0078y only 2. v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected. chapter 23 pd78f0078, 78f0078y 445 user s manual u14260ej3v1ud 23.3.3 on-board pin processing when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. chapter 23 pd78f0078, 78f0078y 446 user s manual u14260ej3v1ud (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection with the other device or set the other device to the output high impedance status. figure 23-7. signal conflict (input pin of serial interface) (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, which may cause an abnormal operation. to prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. figure 23-8. abnormal operation of other device input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. pd78f0078, 78f0078y if the signal output by the pd78f0078, 78f0078y affects another device in the flash memory programming mode, isolate the signals of the other device. if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f0078, 78f0078y pd78f0078, 78f0078y pin connection pin of dedicated flash programmer other device input pin pin connection pin of dedicated flash programmer other device input pin chapter 23 pd78f0078, 78f0078y 447 user s manual u14260ej3v1ud chapter 23 pd78f0078, 78f0078y 448 user s manual u14260ej3v1ud 23.3.4 connection of adapter for flash writing the following shows the recommended connection example when the adapter for flash writing is used. figure 23-10. wiring example for adapter for flash writing with 3-wire serial i/o (sio3) gnd vdd lvdd (vpp2) si so sck clk /reset v pp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 chapter 23 pd78f0078, 78f0078y 449 user s manual u14260ej3v1ud figure 23-11. wiring example for adapter for flash writing with 3-wire serial i/o (sio3) with handshake gnd vdd lvdd (vpp2) si so sck clk /reset v pp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 chapter 23 pd78f0078, 78f0078y 450 user s manual u14260ej3v1ud figure 23-12. wiring example for adapter for flash writing with uart (uart0) gnd vdd lvdd (vpp2) si so sck clk /reset v pp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 chapter 23 pd78f0078, 78f0078y 451 user s manual u14260ej3v1ud figure 23-13. wiring example for adapter for flash writing with i 2 c bus (iic0) ( pd78f0078y only) gnd vdd lvdd (vpp2) si so sck clk /reset v pp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 452 user? manual u14260ej3v1ud chapter 24 instruction set this chapter lists each instruction set of the pd780078, 780078y subseries in table form. for details of the operation and operation code of each instruction, refer to the separate document 78k/0 series instructions user? manual (u12326e) . chapter 24 instruction set 453 user? manual u14260ej3v1ud 24.1 legend used in operation list 24.1.1 operand identifiers and specification methods operands are written in the ?perand?column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more methods, select one of them. uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. #: immediate data specification !: absolute address specification $: relative address specification [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 24-1. operand identifiers and specification methods identifier specification method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special function register symbol note sfrp special function register symbol (16-bit manipulatable register, even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even address only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special function register symbols, refer to table 5-3 special function register list . chapter 24 instruction set 454 user? manual u14260ej3v1ud 24.1.2 description of ?peration?column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 24.1.3 description of ?lag operation?column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored chapter 24 instruction set 455 user? manual u14260ej3v1ud 24.2 operation list clocks flag note 1 note 2 zaccy mov r, #byte 2 4 r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) [hl + c], a 1 6 7 + m (hl + c) a xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed. 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 8-bit data transfer chapter 24 instruction set 456 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy movw rp, #word 3 6 rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 3 1 4 ax rp rp, ax note 3 1 4 rp ax ax, !addr16 3 10 12 + 2n ax (addr16) !addr16, ax 3 10 12 + 2m (addr16) ax xchw ax, rp note 3 1 4 ax ? rp add a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 a, cy a + r r, a 2 4 r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) a, [hl + c] 2 8 9 + n a, cy a + (hl + c) addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 a, cy a + r + cy r, a 2 4 r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 16-bit data transfer 8-bit operation chapter 24 instruction set 457 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy sub a, #byte 2 4 a, cy a ?byte saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte a, r note 3 2 4 a, cy a ?r r, a 2 4 r, cy r ?a a, saddr 2 4 5 a, cy a ?(saddr) a, !addr16 3 8 9 + n a, cy a ?(addr16) a, [hl] 1 4 5 + n a, cy a ?(hl) a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) subc a, #byte 2 4 a, cy a ?byte ?cy saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte ?cy a, r note 3 2 4 a, cy a ?r ?cy r, a 2 4 r, cy r ?a ?cy a, saddr 2 4 5 a, cy a ?(saddr) ?cy a, !addr16 3 8 9 + n a, cy a ?(addr16) ?cy a, [hl] 1 4 5 + n a, cy a ?(hl) ?cy a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) ?cy a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) ?cy a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) ?cy and a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands bytes operation instruction group 8-bit operation chapter 24 instruction set 458 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy or a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) xor a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) cmp a, #byte 2 4 a ?byte saddr, #byte 3 6 8 (saddr) ?byte a, r note 3 24 a r r, a 2 4 r ?a a, saddr 2 4 5 a ?(saddr) a, !addr16 3 8 9 + n a ?(addr16) a, [hl] 1 4 5 + n a ?(hl) a, [hl + byte] 2 8 9 + n a ?(hl + byte) a, [hl + b] 2 8 9 + n a ?(hl + b) a, [hl + c] 2 8 9 + n a ?(hl + c) notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands bytes operation instruction group 8-bit operation chapter 24 instruction set 459 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ?word cmpw ax, #word 3 6 ax ?word mulu x 2 16 ax a x divuw c 2 25 ax (quotient), c (remainder) ax c inc r12 r r + 1 saddr 2 4 6 (saddr) (saddr) + 1 dec r12 r r ?1 saddr 2 4 6 (saddr) (saddr) ?1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ?1 ror a, 1 1 2 (cy, a 7 a 0 , a m ?1 a m ) 1 time rol a, 1 1 2 (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ?1 a m ) 1 time rolc a, 1 1 2 (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 ?0 (hl) 3 ?0 , (hl) 7 ?4 a 3 ?0 , (hl) 3 ?0 (hl) 7 ?4 rol4 [hl] 2 10 12 + n + m a 3 ?0 (hl) 7 ?4 , (hl) 3 ?0 a 3 ?0 , (hl) 7 ?4 (hl) 3 ?0 adjba 2 4 decimal adjust accumulator after addition adjbs 2 4 decimal adjust accumulator after subtract mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 7 cy sfr.bit cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 16-bit operation increment/ decrement bcd adjust bit manipu- late multiply/ divide rotate chapter 24 instruction set 460 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw. bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 + n + m (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group bit manipu- late chapter 24 instruction set 461 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy call !addr16 3 7 (sp ?1) (pc + 3) h , (sp ?2) (pc + 3) l , pc addr16, sp sp ?2 callf !addr11 2 5 (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l , pc 15 ?11 00001, pc 10 ?0 addr11, sp sp ?2 callt [addr5] 1 6 (sp ?1) (pc + 1) h , (sp ?2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ?2 brk 1 6 (sp ?1) psw, (sp ?2) (pc + 1) h , (sp ?3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ?3, ie 0 ret 16 pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 retb 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 push psw 1 2 (sp ?1) psw, sp sp ?1 rp 1 4 (sp ?1) rp h , (sp ?2) rp l , sp sp ?2 pop psw 1 2 psw (sp), sp sp + 1 r r r rp 1 4 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 10 sp word sp, ax 2 8 sp ax ax, sp 2 8 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 2 8 pc h a, pc l x bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. uncondi- tional branch stack manipu- late conditional branch call/return mnemonic operands bytes operation instruction group chapter 24 instruction set 462 user? manual u14260ej3v1ud clocks flag note 1 note 2 zaccy bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 b b ?1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ?, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 10 (saddr) (saddr) ?1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 rbs1, 0 n nop 1 2 no operation ei 2 6 ie 1 (enable interrupt) di 2 6 ie 0 (disable interrupt) halt 2 6 set halt mode stop 2 6 set stop mode notes 1. when the internal high-speed ram area is accessed or an instruction with no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks applies when there is a program in the internal rom. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group cpu control condi- tional branch chapter 24 instruction set 463 user? manual u14260ej3v1ud 24.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz chapter 24 instruction set 464 user? manual u14260ej3v1ud note except r = a second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw chapter 24 instruction set 465 user? manual u14260ej3v1ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand #word ax rp note sfrp saddrp !addr16 sp none first operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 chapter 24 instruction set 466 user? manual u14260ej3v1ud (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand ax !addr16 !addr11 [addr5] $addr16 first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 467 users manual u14260ej3v1ud chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) target products: pd780076, 780078, 78f0078 for which orders were received after february 1, 2002 (products with a rank note other than k) note the rank is indicated by the 5th digit from the left in the lot number marked on the package. absolute maximum ratings (t a = 25 c) parameter supply voltage input voltage output voltage analog input voltage output current, high output current, low operating ambient temperature storage temperature symbol v dd v pp av ref av ss v i1 v i2 v o v an i oh i ol t a t stg conditions pd78f0078 only, note 2 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, x1, x2, xt1, xt2, reset p30 to p33 n-ch open- no pull-up resistor drain pull-up resistor p10 to p17 analog input pin per pin total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 total for p20 to p25, p30 to p36 per pin for p00 to p03, p20 to p25, p34 to p36, p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 total for p00 to p03, p40 to p47, p64 to p67, p70 to p75, p80 total for p20 to p25 total for p30 to p36 total for p50 to p57 during normal operation during flash memory programming pd780076, 780078 pd78f0078 ratings ? 0.3 to +6.5 ? 0.5 to +10.5 ? 0.3 to v dd + 0.3 note 1 ? 0.3 to +0.3 ? 0.3 to v dd + 0.3 note 1 ? 0.3 to +6.5 ? 0.3 to v dd + 0.3 note 1 ? 0.3 to v dd + 0.3 note 1 av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 ? 10 ? 15 ? 15 20 30 50 20 100 100 ? 40 to +85 +10 to +40 ? 65 to +150 ? 40 to +125 unit v v v v v v v v v ma ma ma ma ma ma ma ma ma c c c c note 1. 6.5 v or below ( note 2 is explained on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. lot number year code rank week code 468 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). ?when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75, p80 p30 to p33 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 2.7 v v dd 0 v 0 v v pp 2.7 v a b 469 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 oscillation 4.0 v v dd 5.5 v 10 ms stabilization time note 2 1.8 v v dd < 4.0 v 30 external x1 input 4.5 v v dd 5.5 v 1.0 12.0 mhz clock frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 x1 input 4.5 v v dd 5.5 v 38 500 ns high-/low-level width 3.0 v v dd < 4.5 v 50 500 (t xh , t xl ) 1.8 v v dd < 3.0 v 85 500 x2 x1 c2 rd c1 x1 v ss1 x2 c2 rd c1 x1 v ss1 x2 470 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 4.0 v v dd 5.5 v 1.8 v v dd < 4.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s xt1 xt2 c3 xt2 xt1 v ss1 rd c4 471 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud recommended oscillator constant (1) pd780076, 780078 (a) main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) rd (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 150 150 0 1.8 5.5 co., ltd. csbla1m00j58 1.00 150 150 0 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstls5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 cstce10m0g52 10.00 on-chip on-chip 0 4.5 5.5 cstls10m0g53 10.00 on-chip on-chip 0 4.5 5.5 cstce12m0g52 12.00 on-chip on-chip 0 4.5 5.5 cstla12m0t55 12.00 on-chip on-chip 0 4.5 5.5 tdk ccr3.5mc5 3.58 on-chip on-chip 0 1.8 5.5 ccr4.0mc5 4.00 on-chip on-chip 0 1.8 5.5 ccr4.19mc5 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc5 5.00 on-chip on-chip 0 2.7 5.5 ccr6.0mc5 6.00 on-chip on-chip 0 2.7 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 3.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 3.0 5.5 ccr10.0mc5 10.00 on-chip on-chip 0 4.5 5.5 ccr12.0mc5 12.00 on-chip on-chip 0 4.5 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078 subseries within the specifications of the dc and ac characteristics. 472 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (1) pd780076, 780078 (b) main system clock: crystal resonator (t a = ?0 to +70 c) (c) subsystem clock: crystal resonator (t a = ?0 to +85 c) caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078 subseries within the specifications of the dc and ac characteristics. manufacturer kinseki, ltd. part number hc-49/u-s frequency (mhz) 4.19 8.38 c1 (pf) 18 27 c2 (pf) 18 27 min. (v) 1.9 3.0 max. (v) 5.5 5.5 recommended circuit constant oscillation voltage range rd (k ? ) 4.7 0 manufacturer seiko epson corporation part number c-022rx mc-206 mc-306 frequency (khz) 32.768 32.768 32.768 c1 (pf) 15 15 15 c2 (pf) 15 15 15 min. (v) 1.8 1.8 1.8 max. (v) 5.5 5.5 5.5 recommended circuit constant oscillation voltage range rd (k ? ) 330 330 330 473 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (2) pd78f0078 main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 3.3 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 3.3 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstls5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 cstce10m0g52 10.00 on-chip on-chip 0 4.5 5.5 cstls10m0g53 10.00 on-chip on-chip 0 4.5 5.5 cstls10m0g55093 10.00 on-chip on-chip 0 4.5 5.5 cstce12m0g52 12.00 on-chip on-chip 0 4.5 5.5 cstla12m0t55 12.00 on-chip on-chip 0 4.5 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078 subseries within the specifications of the dc and ac characteristics. remark for the resonator selection and oscillator constant, users are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 474 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, i oh per pin C1 ma high all pins C15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75, p80 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34 to p36, p70 to p75, p80, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd C 0.5 v dd v 1.8 v v dd < 2.7 v v dd C 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34 to p36, p70 to p75, p80, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v (n-ch open-drain) 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = C1 ma v dd C 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = C100 a v dd C 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low i ol = 15 ma v ol2 p50 to p57 4.0 v v dd 5.5 v, 0.4 2.0 v i ol = 15 ma v ol3 p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75, p80 i ol = 1.6 ma v ol4 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 475 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, C3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lil2 x1, x2, xt1, xt2 C20 a i lil3 p30 to p33 C3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v C3 a current, low mask option r 1 v in = 0 v, 15 30 90 k ? pull-up resistance p30, p31, p32, p33 (mask rom version only) software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 v pp (ic) v pp1 during normal operation 0 0.2v dd v power supply voltage remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 476 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (1) pd780076, 780078 parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 12.0 mhz v dd = 5.0 v 10% note 3 when a/d converter is 9.0 18.0 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 10.0 20.0 ma operating 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11.0 ma crystal oscillation stopped operating mode when a/d converter is 6.5 13.0 ma operating v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 3.5 7.0 ma stopped when a/d converter is 4.5 9.0 ma operating 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2.0 4.0 ma crystal oscillation stopped operating mode when a/d converter is 3.0 6.0 ma operating v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating i dd2 12.0 mhz v dd = 5.0 v 10% note 3 when peripheral functions 2.5 5.0 ma crystal oscillation are stopped halt mode when peripheral functions 11.5 ma are operating 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.7 1.4 ma are stopped when peripheral functions 4.5 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 stop mode note 7 v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a 477 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud notes 1. total current through the internal power supply (v dd0 , v dd1 ). 2. i dd1 includes the peripheral operating current (except the current through the pull-up resistors of ports). 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column shows the specifications when v dd = 3.0 v. 7. when the main system clock and subsystem clock are stopped. 478 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (2) pd78f0078 parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 12.0 mhz v dd = 5.0 v 10% note 3 when a/d converter is 17.0 34.0 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 18.0 36.0 ma operating 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 10.5 21.0 ma crystal oscillation stopped operating mode when a/d converter is 11.5 23.0 ma operating v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 7.0 14.0 ma stopped when a/d converter is 8.0 16.0 ma operating 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 4.5 9.0 ma crystal oscillation stopped operating mode when a/d converter is 5.5 11.0 ma operating v dd = 2.0 v 10% note 4 when a/d converter is 1.0 2.0 ma stopped when a/d converter is 2.0 6.0 ma operating i dd2 12.0 mhz v dd = 5.0 v 10% note 3 when peripheral functions 2.5 5.0 ma crystal oscillation are stopped halt mode when peripheral functions 11.5 ma are operating 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.2 2.4 ma crystal oscillation are stopped halt mode when peripheral functions 5.0 ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.7 1.4 ma are stopped when peripheral functions 4.5 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.4 0.8 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.2 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 115 230 a operating mode note 5 v dd = 3.0 v 10% 95 190 a v dd = 2.0 v 10% 75 150 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 stop mode note 7 v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a 479 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud notes 1. total current through the internal power supply (v dd0 , v dd1 ). 2. i dd1 includes the peripheral operating current (except the current through the pull-up resistors of ports). 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column shows the specifications when v dd = 3.0 v. 7. when the main system clock and subsystem clock are stopped. 480 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with 4.5 v v dd 5.5 v 0.166 16 s (min. instruction main system clock 3.0 v v dd < 4.5 v 0.238 16 s execution time) 2.7 v v dd < 3.0 v 0.4 16 s 1.8 v v dd < 2.7 v 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti000, ti010, ti001, t tih0 , t til0 3.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s ti011 input high-/low- 2.7 v v dd < 3.0 v 2/f sam + 0.2 note 2 s level width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 s width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm000, prm010) of prescaler mode register 00 (prm00). selection of f sam = f x /2, f x /8, f x /512 is possible using bits 0 and 1 (prm001, prm011) of prescaler mode register 01 (prm01). however, if the ti000 or ti001 valid edge is selected as the count clock, the value becomes f sam = f x /8. 481 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.166 0.1 supply voltage v dd [v] cycle time t cy [s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 4.5 operation guaranteed range 16.0 482 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 4.0 to 5.5 v) (1/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy C 54 ns t add2 (3 + 2n)t cy C 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 87 ns t rdd2 (3 + 2n)t cy C 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 33 ns t rdl2 (2.5 + 2n)t cy C 33 ns input time from rd to wait t rdwt1 t cy C 43 ns t rdwt2 t cy C 43 ns input time from wr to wait t wrwt t cy C 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy C 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy C 15 ns delay time from t rdast 0.8t cy C 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy C 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy C 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns caution t cy can only be used when the min. value is 0.238 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 483 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 2.7 to 4.0 v) (2/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy C 108 ns t add2 (3 + 2n)t cy C 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy C 148 ns t rdd2 (3 + 2n)t cy C 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 40 ns t rdl2 (2.5 + 2n)t cy C 40 ns input time from rd to wait t rdwt1 t cy C 75 ns t rdwt2 t cy C 60 ns input time from wr to wait t wrwt t cy C 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy C 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy C 30 ns delay time from t rdast 0.8t cy C 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy C 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy C 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns caution t cy can only be used when the min. value is 0.4 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 484 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 1.8 to 2.7 v) (3/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy C 233 ns t add2 (3 + 2n)t cy C 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy C 325 ns t rdd2 (3 + 2n)t cy C 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 92 ns t rdl2 (2.5 + 2n)t cy C 92 ns input time from rd to wait t rdwt1 t cy C 350 ns t rdwt2 t cy C 132 ns input time from wr to wait t wrwt t cy C 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy C 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy C 60 ns delay time from t rdast 0.8t cy C 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy C 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy C 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns caution t cy can only be used when the min. value is 1.6 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 485 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (3) serial interface (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) (a) sio3 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy1 4.5 v v dd 5.5 v 666 ns 3.0 v v dd < 4.5 v 954 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/ t kh1 , t kl1 3.0 v v dd 5.5 v t kcy1 /2 C 50 ns low-level width 1.8 v v dd < 3.0 v t kcy1 /2 C 100 ns si3 setup time t sik1 3.0 v v dd 5.5 v 100 ns (to sck3 ) 2.7 v v dd < 3.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3 hold time t ksi1 4.5 v v dd 5.5 v 300 ns (from sck3 ) 1.8 v v dd < 4.5 v 400 ns delay time from t kso1 c = 100 pf note 4.5 v v dd 5.5 v 200 ns sck3 to so3 output 1.8 v v dd < 4.5 v 300 ns note c is the load capacitance of the sck3 and so3 output lines. (b) sio3 3-wire serial i/o mode (sck3 ... external clock input) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy2 4.5 v v dd 5.5 v 666 ns 3.0 v v dd < 4.5 v 800 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/ t kh2 , t kl2 4.5 v v dd 5.5 v 333 ns low-level width 3.0 v v dd < 4.5 v 400 ns 2.7 v v dd < 3.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3 setup time t sik2 100 ns (to sck3 ) si3 hold time t ksi2 4.5 v v dd 5.5 v 300 ns (from sck3 ) 1.8 v v dd < 4.5 v 400 ns delay time from t kso2 c = 100 pf note 4.5 v v dd 5.5 v 200 ns sck3 to so3 output 1.8 v v dd < 4.5 v 300 ns note c is the load capacitance of the so3 output line. 486 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (c) csi1 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy3 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh3 , t kl3 4.0 v v dd 5.5 v t kcy3 /2 C 5 ns width 2.7 v v dd < 4.0 v t kcy3 /2 C 20 ns 1.8 v v dd < 2.7 v t kcy3 /2 C 30 ns si1 setup time t sik3 25 ns (to sck1 ) si1 hold time t ksi3 110 ns (from sck1 ) delay time from sck1 t kso3 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the sck1 and so1 output lines. (d) csi1 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy4 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh4 , t kl4 4.0 v v dd 5.5 v 100 ns width 2.7 v v dd < 4.0 v 250 ns 1.8 v v dd < 2.7 v 500 ns si1 setup time t sik4 25 ns (to sck1 ) si1 hold time t ksi4 110 ns (from sck1 ) delay time from sck1 t kso4 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the so1 output line. (e) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 187500 bps 3.0 v v dd < 4.5 v 131031 bps 2.7 v v dd < 3.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps 487 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (f) uart0 (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy5 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level t kh5 , t kl5 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (g) uart0 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps bit rate tolerance 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate (h) uart2 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps 2.7 v v dd < 4.0 v 156250 bps 1.8 v v dd < 2.7 v 62500 bps (i) uart2 (external clock input) parameter symbol conditions min. typ. max. unit asck2 cycle time t kcy6 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck2 high-/low-level t kh6 , t kl6 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.0 v 39063 bps 1.8 v v dd < 2.7 v 19531 bps 488 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (j) uart2 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps bit rate tolerance 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate a/d converter characteristics (t a = 40 to +85 c, 2.2 v av ref v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 2.2 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.5 v av ref 5.5 v 12 96 s 4.0 v av ref < 4.5 v 14 96 s 2.7 v av ref < 4.0 v 17 96 s 2.2 v av ref < 2.7 v 28 96 s zero-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr full-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr integral linear error 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 2.2 v av ref < 2.7 v 8.5 lsb differential linear error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 2.2 v av ref < 2.7 v 3.5 lsb analog input impedance during sampling 100 k ? other than during sampling 10 m ? analog input voltage v ain 0av ref v av ref resistance r ref during a/d conversion 20 40 k ? note overall error excluding quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. remark fsr: full-scale range 489 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) and 0.1 30 a supply current feedback resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx s wait time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). flash memory programming characteristics (t a = +10 to +40 c, v dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 4.5 v v dd 5.5 v 1.0 10.0 mhz 3.0 v v dd < 4.5 v 1.0 8.38 mhz 2.7 v v dd < 3.0 v 1.0 5.00 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when f x = 10.0 mhz v dd = 5.0 v 10% 29 ma v pp = v pp2 f x = 8.38 mhz v dd = 5.0 v 10% 24 ma v dd = 3.0 v 10% 17 ma v pp supply current i pp when v pp = v pp2 75 100 ma step erase time note 1 t er 0.99 1.0 1.01 s overall erase time per area note 2 t era when step erase time = 1 s 20 s/area step write time t wr 50 100 s overall write time per word note 3 t wrw when step write time = 100 s 1000 s number of rewrites per area note 4 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/area notes 1. the recommended setting value of the step erase time is 1 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 4. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites 490 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 1.0 s v pp pulse input start time from t rp 1.0 s reset v pp pulse high-/low-level width t pw 8.0 s v pp pulse input end time from t rpe 20 ms reset v pp pulse low-level input voltage v ppl 0.8v dd v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v 491 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud timing chart ac timing test points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti000, ti010, ti001, ti011 1/f ti5 t tih5 t til5 ti50, ti51 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 492 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud t rsl reset intp0 to intp3 t intl t inth interrupt request input timing reset input timing 493 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh 494 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 495 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr 496 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): t kcyn t khn t kln asck0, asck2 t kcyn t kln t khn sck1, sck3 si1, si3 so1, so3 t sikn t ksin t kson input data output data remark n = 1 to 4 remark n = 5, 6 497 chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) users manual u14260ej3v1ud flash write mode setting timing notes 1. 3-wire serial i/o (sio3) type 2. uart (uart0) type 3. handshake (when 3-wire serial i/o (sio3) type is used) v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe 0 v sck3 note 1 0 v 0 v 0 v si3 note 1 /rxd0 note 2 so3 note 1 /txd0 note 2 p31 (hs) note 3 reset command v il v il 498 users manual u14260ej3v1ud chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) target products: pd780076y, 780078y, 78f0078y for which orders were received after february 1, 2002 (products with a rank note other than k) note the rank is indicated by the 5th digit from the left in the lot number marked on the package. absolute maximum ratings (t a = 25 c) parameter supply voltage input voltage output voltage analog input voltage output current, high output current, low operating ambient temperature storage temperature symbol v dd v pp av ref av ss v i1 v i2 v o v an i oh i ol t a t stg conditions pd78f0078y only, note 2 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, x1, x2, xt1, xt2, reset p30 to p33 n-ch open- no pull-up resistor drain pull-up resistor p10 to p17 analog input pin per pin total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 total for p20 to p25, p30 to p36 per pin for p00 to p03, p20 to p25, p34 to p36, p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 total for p00 to p03, p40 to p47, p64 to p67, p70 to p75, p80 total for p20 to p25 total for p30 to p36 total for p50 to p57 during normal operation during flash memory programming pd780076y, 780078y pd78f0078y ratings ? 0.3 to +6.5 ? 0.5 to +10.5 ? 0.3 to v dd + 0.3 note 1 ? 0.3 to +0.3 ? 0.3 to v dd + 0.3 note 1 ? 0.3 to +6.5 ? 0.3 to v dd + 0.3 note 1 ? 0.3 to v dd + 0.3 note 1 av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 ? 10 ? 15 ? 15 20 30 50 20 100 100 ? 40 to +85 +10 to +40 ? 65 to +150 ? 40 to +125 unit v v v v v v v v v ma ma ma ma ma ma ma ma ma c c c c lot number year code rank week code note 1. 6.5 v or below ( note 2 is explained on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 499 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). ?when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75, p80 p30 to p33 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 2.7 v v dd 0 v 0 v v pp 2.7 v a b 500 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 3.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 3.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 3.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 3.0 v 1.0 5.0 oscillation 3.0 v v dd 5.5 v 10 ms stabilization time note 2 1.8 v v dd < 3.0 v 30 external x1 input 3.0 v v dd 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 1.8 v v dd < 3.0 v 1.0 5.0 x1 input 3.0 v v dd 5.5 v 50 500 ns high-/low-level width (t xh , t xl ) 1.8 v v dd < 3.0 v 85 500 x2 x1 c2 rd c1 x1 v ss1 x2 c2 rd c1 x1 v ss1 x2 501 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 3.0 v v dd 5.5 v 1.8 v v dd < 3.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s xt1 xt2 c3 xt2 xt1 v ss1 rd c4 502 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud recommended oscillator constant (1) pd780076y, 780078y (a) main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) rd (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 150 150 0 1.8 5.5 co., ltd. csbla1m00j58 1.00 150 150 0 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstls5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 tdk ccr3.5mc5 3.58 on-chip on-chip 0 1.8 5.5 ccr4.0mc5 4.00 on-chip on-chip 0 1.8 5.5 ccr4.19mc5 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc5 5.00 on-chip on-chip 0 2.7 5.5 ccr6.0mc5 6.00 on-chip on-chip 0 2.7 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 3.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 3.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078y subseries within the specifications of the dc and ac characteristics. 503 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (1) pd780076y, 780078y (b) main system clock: crystal resonator (t a = ?0 to +70 c) (c) subsystem clock: crystal resonator (t a = ?0 to +85 c) caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078y subseries within the specifications of the dc and ac characteristics. manufacturer kinseki, ltd. part number hc-49/u-s frequency (mhz) 4.19 8.38 c1 (pf) 18 27 c2 (pf) 18 27 min. (v) 1.9 3.0 max. (v) 5.5 5.5 recommended circuit constant oscillation voltage range rd (k ? ) 4.7 0 manufacturer seiko epson corporation part number c-022rx mc-206 mc-306 frequency (khz) 32.768 32.768 32.768 c1 (pf) 15 15 15 c2 (pf) 15 15 15 min. (v) 1.8 1.8 1.8 max. (v) 5.5 5.5 5.5 recommended circuit constant oscillation voltage range rd (k ? ) 330 330 330 504 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (2) pd78f0078y main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 3.3 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 3.3 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstls5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078y subseries within the specifications of the dc and ac characteristics. remark for the resonator selection and oscillator constant, users are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 505 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, i oh per pin C1 ma high all pins C15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75, p80 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34 to p36, p70 to p75, p80, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd C 0.5 v dd v 1.8 v v dd < 2.7 v v dd C 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34 to p36, p70 to p75, p80, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v (n-ch open-drain) 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = C1 ma v dd C 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = C100 a v dd C 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low i ol = 15 ma v ol2 p50 to p57 4.0 v v dd 5.5 v, 0.4 2.0 v i ol = 15 ma v ol3 p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75, p80 i ol = 1.6 ma v ol4 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 506 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, C3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lil2 x1, x2, xt1, xt2 C20 a i lil3 p30 to p33 C3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v C3 a current, low mask option r 1 v in = 0 v, 15 30 90 k ? pull-up resistance p30, p31 (mask rom version only) software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 v pp (ic) v pp1 during normal operation 0 0.2v dd v power supply voltage remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 507 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (1) pd780076y, 780078y parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11.0 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13.0 ma operating v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 3.5 7.0 ma stopped when a/d converter is 4.5 9.0 ma operating 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2.0 4.0 ma crystal oscillation stopped operating mode when a/d converter is 3.0 6.0 ma operating v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.7 1.4 ma are stopped when peripheral functions 4.5 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 stop mode note 7 v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ). 2. i dd1 includes the peripheral operating current (except the current through the pull-up resistors of ports). 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column shows the specifications when v dd = 3.0 v. 7. when the main system clock and subsystem clock are stopped. 508 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (2) pd78f0078y parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 10.5 21.0 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 11.5 23.0 ma operating v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 7.0 14.0 ma stopped when a/d converter is 8.0 16.0 ma operating 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 4.5 9.0 ma crystal oscillation stopped operating mode when a/d converter is 5.5 11.0 ma operating v dd = 2.0 v 10% note 4 when a/d converter is 1.0 2.0 ma stopped when a/d converter is 2.0 6.0 ma operating i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.2 2.4 ma crystal oscillation are stopped halt mode when peripheral functions 5.0 ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.7 1.4 ma are stopped when peripheral functions 4.5 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.4 0.8 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.2 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 115 230 a operating mode note 5 v dd = 3.0 v 10% 95 190 a v dd = 2.0 v 10% 75 150 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 stop mode note 7 v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ). 2. i dd1 includes the peripheral operating current (except the current through the pull-up resistors of ports). 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column shows the specifications when v dd = 3.0 v. 7. when the main system clock and subsystem clock are stopped. 509 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with 3.0 v v dd 5.5 v 0.238 16 s (min. instruction main system clock 2.7 v v dd < 3.0 v 0.4 16 s execution time) 1.8 v v dd < 2.7 v 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti000, ti010, ti001, t tih0 , t til0 3.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s ti011 input high-/low- 2.7 v v dd < 3.0 v 2/f sam + 0.2 note 2 s level width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 s width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm000, prm010) of prescaler mode register 00 (prm00). selection of f sam = f x /2, f x /8, f x /512 is possible using bits 0 and 1 (prm001, prm011) of prescaler mode register 01 (prm01). however, if the ti000 or ti001 valid edge is selected as the count clock, the value becomes f sam = f x /8. 510 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.1 supply voltage v dd [v] cycle time t cy [s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 operation guaranteed range 16.0 511 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 4.0 to 5.5 v) (1/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy C 54 ns t add2 (3 + 2n)t cy C 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 87 ns t rdd2 (3 + 2n)t cy C 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 33 ns t rdl2 (2.5 + 2n)t cy C 33 ns input time from rd to wait t rdwt1 t cy C 43 ns t rdwt2 t cy C 43 ns input time from wr to wait t wrwt t cy C 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy C 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy C 15 ns delay time from t rdast 0.8t cy C 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy C 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy C 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns caution t cy can only be used when the min. value is 0.238 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 512 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 2.7 to 4.0 v) (2/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy C 108 ns t add2 (3 + 2n)t cy C 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy C 148 ns t rdd2 (3 + 2n)t cy C 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 40 ns t rdl2 (2.5 + 2n)t cy C 40 ns input time from rd to wait t rdwt1 t cy C 75 ns t rdwt2 t cy C 60 ns input time from wr to wait t wrwt t cy C 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy C 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy C 30 ns delay time from t rdast 0.8t cy C 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy C 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy C 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns caution t cy can only be used when the min. value is 0.4 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 513 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 1.8 to 2.7 v) (3/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy C 233 ns t add2 (3 + 2n)t cy C 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy C 325 ns t rdd2 (3 + 2n)t cy C 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 92 ns t rdl2 (2.5 + 2n)t cy C 92 ns input time from rd to wait t rdwt1 t cy C 350 ns t rdwt2 t cy C 132 ns input time from wr to wait t wrwt t cy C 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy C 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy C 60 ns delay time from t rdast 0.8t cy C 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy C 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy C 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns caution t cy can only be used when the min. value is 1.6 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 514 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (3) serial interface (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) (a) sio3 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy1 3.0 v v dd 5.5 v 954 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/ t kh1 , t kl1 3.0 v v dd 5.5 v t kcy1 /2 C 50 ns low-level width 1.8 v v dd < 3.0 v t kcy1 /2 C 100 ns si3 setup time t sik1 3.0 v v dd 5.5 v 100 ns (to sck3 ) 2.7 v v dd < 3.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3 hold time t ksi1 400 ns (from sck3 ) delay time from t kso1 c = 100 pf note 300 ns sck3 to so3 output note c is the load capacitance of the sck3 and so3 output lines. (b) sio3 3-wire serial i/o mode (sck3 ... external clock input) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy2 3.0 v v dd 5.5 v 800 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/ t kh2 , t kl2 3.0 v v dd 5.5 v 400 ns low-level width 2.7 v v dd < 3.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3 setup time t sik2 100 ns (to sck3 ) si3 hold time t ksi2 400 ns (from sck3 ) delay time from t kso2 c = 100 pf note 300 ns sck3 to so3 output note c is the load capacitance of the so3 output line. 515 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (c) csi1 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy3 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh3 , t kl3 4.0 v v dd 5.5 v t kcy3 /2 C 5 ns width 2.7 v v dd < 4.0 v t kcy3 /2 C 20 ns 1.8 v v dd < 2.7 v t kcy3 /2 C 30 ns si1 setup time t sik3 25 ns (to sck1 ) si1 hold time t ksi3 110 ns (from sck1 ) delay time from sck1 t kso3 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the sck1 and so1 output lines. (d) csi1 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy4 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh4 , t kl4 4.0 v v dd 5.5 v 100 ns width 2.7 v v dd < 4.0 v 250 ns 1.8 v v dd < 2.7 v 500 ns si1 setup time t sik4 25 ns (to sck1 ) si1 hold time t ksi4 110 ns (from sck1 ) delay time from sck1 t kso4 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the so1 output line. (e) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 3.0 v v dd 5.5 v 131031 bps 2.7 v v dd < 3.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps 516 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (f) uart0 (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy5 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level t kh5 , t kl5 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (g) uart0 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps bit rate tolerance 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate (h) uart2 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps 2.7 v v dd < 4.0 v 156250 bps 1.8 v v dd < 2.7 v 62500 bps (i) uart2 (external clock input) parameter symbol conditions min. typ. max. unit asck2 cycle time t kcy6 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck2 high-/low-level t kh6 , t kl6 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.0 v 39063 bps 1.8 v v dd < 2.7 v 19531 bps 517 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud (j) uart2 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps bit rate tolerance 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate (k) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f scl 0 100 0 400 khz bus free time t buf 4.7 1.3 s (between stop and start condition) hold time note 1 t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s start/restart condition setup time t su:sta 4.7 0.6 s data hold time cbus compatible master t hd:dat 5.0 s i 2 c bus 0 note 2 0 note 2 0.9 note 3 s data setup time t su:dat 250 100 note 4 ns sda0 and scl0 signal rise time t r 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 0.6 s capacitive load per each bus line cb 400 400 pf spike pulse width controlled by input filter t sp 0 50ns notes 1. on a start condition, the first clock pulse is generated after the hold period. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to internally provide an sda0 signal (with v ihmin. of the scl0 signal) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low hold time (t low ), only the maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in a standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. ? if the device does not extend the scl0 signal low state hold time t su:dat 250 ns ? if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb: total capacitance per bus line (unit: pf) 518 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud a/d converter characteristics (t a = 40 to +85 c, 2.2 v av ref v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 2.2 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.0 v av ref 5.5 v 14 96 s 2.7 v av ref < 4.0 v 17 96 s 2.2 v av ref < 2.7 v 28 96 s zero-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr full-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr integral linear error 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 2.2 v av ref < 2.7 v 8.5 lsb differential linear error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 2.2 v av ref < 2.7 v 3.5 lsb analog input impedance during sampling 100 k ? other than during sampling 10 m ? analog input voltage v ain 0av ref v av ref resistance r ref during a/d conversion 20 40 k ? note overall error excluding quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. remark fsr: full-scale range data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) and 0.1 30 a supply current feedback resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx s wait time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). 519 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud flash memory programming characteristics (t a = +10 to +40 c, v dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 3.0 v v dd 5.5 v 1.0 8.38 mhz 2.7 v v dd < 3.0 v 1.0 5.00 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when f x = 8.38 mhz v dd = 5.0 v 10% 24 ma v pp = v pp2 v dd = 3.0 v 10% 17 ma f x = 5.00 mhz v dd = 3.0 v 10% 12 ma v pp supply current i pp when v pp = v pp2 75 100 ma step erase time note 1 t er 0.99 1.0 1.01 s overall erase time per area note 2 t era when step erase time = 1 s 20 s/area step write time t wr 50 100 s overall write time per word note 3 t wrw when step write time = 100 s 1000 s number of rewrites per area note 4 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/area notes 1. the recommended setting value of the step erase time is 1 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 4. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 1.0 s v pp pulse input start time from t rp 1.0 s reset v pp pulse high-/low-level width t pw 8.0 s v pp pulse input end time from t rpe 20 ms reset v pp pulse low-level input voltage v ppl 0.8v dd v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v 520 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud timing chart ac timing test points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti000, ti010, ti001, ti011 1/f ti5 t tih5 t til5 ti50, ti51 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 521 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud t rsl reset intp0 to intp3 t intl t inth interrupt request input timing reset input timing 522 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh 523 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 524 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr 525 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): t kcyn t khn t kln asck0, asck2 i 2 c bus mode: scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r t low stop condition start condition stop condition restart condition remark n = 1 to 4 remark n = 5, 6 t kcyn t kln t khn sck1, sck3 si1, si3 so1, so3 t sikn t ksin t kson input data output data 526 chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) users manual u14260ej3v1ud flash write mode setting timing notes 1. 3-wire serial i/o (sio3) type 2. i 2 c bus (iic0) type 3. uart (uart0) type 4. handshake (when 3-wire serial i/o (sio3) type is used) v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe 0 v sck3 note 1 /scl0 note 2 0 v 0 v 0 v si3 note 1 /rxd0 note 3 so3 note 1 /txd0 note 3 /sda0 note 2 p31 (hs) note 4 reset command v il v il 527 user? manual u14260ej3v1ud chapter 27 electrical specifications (conventional products) target products: pd780076, 780078, 780076y, 780078y, 78f0078, 78f0078y for which orders were received before january 31, 2002 (products with a rank note k) note the rank is indicated by the 5th digit from the left in the lot number marked on the package. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v v pp pd78f0078, 78f0078y only, note 2 ?.5 to +10.5 v av ref ?.3 to v dd + 0.3 note 1 v av ss ?.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, ?.3 to v dd + 0.3 note 1 v p50 to p57, p64 to p67, p70 to p75, p80, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open-drain no pull-up resistor ?.3 to +6.5 v pull-up resistor ?.3 to v dd + 0.3 note 1 v output voltage v o ?.3 to v dd + 0.3 note 1 v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref + 0.3 note 1 v and ?.3 to v dd + 0.3 note 1 output current, i oh per pin ?0 ma high total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 ?5 ma total for p20 to p25, p30 to p36 ?5 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, p40 to 20 ma low p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75, p80 50 ma total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a during normal operation ?0 to +85 c temperature during flash memory programming +10 to +40 c storage t stg pd780076, 780078, 780076y, 780078y ?5 to +150 c temperature pd78f0078, 78f0078y ?0 to +125 c note 1. 6.5 v or below ( note 2 is explained on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. lot number year code rank week code 528 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud note 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75, p80 p30 to p33 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 2.7 v v dd 0 v 0 v v pp 2.7 v a b 529 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 4.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 oscillation 4.0 v v dd 5.5 v 10 ms 1.8 v v dd < 4.0 v 30 stabilization time note 2 external x1 input 4.0 v v dd 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 x1 input 4.0 v v dd 5.5 v 50 500 ns high-/low-level width (t xh , t xl ) 1.8 v v dd < 4.0 v 85 500 x2 x1 c2 rd c1 x1 v ss1 x2 c2 rd c1 x1 v ss1 x2 530 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 4.0 v v dd 5.5 v 1.8 v v dd < 4.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s xt1 xt2 c3 xt2 xt1 v ss1 rd c4 531 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud recommended oscillator constant (1) pd780076, 780078, 780076y, 780078y (a) main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) rd (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 150 150 0 1.8 5.5 co., ltd. csbla1m00j58 1.00 150 150 0 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstls5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 tdk ccr3.5mc5 3.58 on-chip on-chip 0 1.8 5.5 ccr4.0mc5 4.00 on-chip on-chip 0 1.8 5.5 ccr4.19mc5 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc5 5.00 on-chip on-chip 0 2.7 5.5 ccr6.0mc5 6.00 on-chip on-chip 0 2.7 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 3.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 3.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078, 780078y subseries within the specifications of the dc and ac characteristics. 532 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (1) pd780076, 780078, 780076y, 780078y (b) main system clock: crystal resonator (t a = ?0 to +70 c) (c) subsystem clock: crystal resonator (t a = ?0 to +85 c) caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078, 780078y subseries within the specifications of the dc and ac characteristics. manufacturer kinseki, ltd. part number hc-49/u-s frequency (mhz) 4.19 8.38 c1 (pf) 18 27 c2 (pf) 18 27 min. (v) 1.9 3.0 max. (v) 5.5 5.5 recommended circuit constant oscillation voltage range rd (k ? ) 4.7 0 manufacturer seiko epson corporation part number c-022rx mc-206 mc-306 frequency (khz) 32.768 32.768 32.768 c1 (pf) 15 15 15 c2 (pf) 15 15 15 min. (v) 1.8 1.8 1.8 max. (v) 5.5 5.5 5.5 recommended circuit constant oscillation voltage range rd (k ? ) 330 330 330 533 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (2) pd78f0078, 78f0078y main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 3.3 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 3.3 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstls5m00g53 5.00 on-chip on-chip 0 2.7 5.5 cstce8m00g52 8.00 on-chip on-chip 0 3.0 5.5 cstls8m00g53 8.00 on-chip on-chip 0 3.0 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780078, 780078y subseries within the specifications of the dc and ac characteristics. remark for the resonator selection and oscillator constant, users are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 534 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, i oh per pin 1ma high all pins 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75, p80 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34 to p36, p70 to p75, p80, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd 0.5 v dd v 1.8 v v dd < 2.7 v v dd 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34 to p36, p70 to p75, p80, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v (n-ch open-drain) 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = 1 ma v dd 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = 100 a v dd 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low i ol = 15 ma v ol2 p50 to p57 4.0 v v dd 5.5 v, 0.4 2.0 v i ol = 15 ma v ol3 p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75, p80 i ol = 1.6 ma v ol4 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 535 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 note 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, 3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lil2 x1, x2, xt1, xt2 20 a i lil3 p30 to p33 note 3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option r 1 v in = 0 v, 15 30 90 k ? pull-up resistance p30, p31, p32 note , p33 note (mask rom version only) software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 v pp (ic) v pp1 during normal operation 0 0.2v dd v power supply voltage note pd780076, 780078 only remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 536 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (1) pd780076, 780078, 780076y, 780078y parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11.0 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13.0 ma operating 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2.0 4.0 ma crystal oscillation stopped operating mode when a/d converter is 3.0 6.0 ma operating v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 stop mode note 6 v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ). 2. i dd1 includes the peripheral operating current (except the current through the pull-up resistors of ports). 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. when the main system clock and subsystem clock are stopped. 537 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (2) pd78f0078, 78f0078y parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 10.5 21.0 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 11.5 23.0 ma operating 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 4.5 9.0 ma crystal oscillation stopped operating mode when a/d converter is 5.5 11.0 ma operating v dd = 2.0 v 10% note 4 when a/d converter is 1.0 2.0 ma stopped when a/d converter is 2.0 6.0 ma operating i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.2 2.4 ma crystal oscillation are stopped halt mode when peripheral functions 5.0 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.4 0.8 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.2 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 115 230 a operating mode note 5 v dd = 3.0 v 10% 95 190 a v dd = 2.0 v 10% 75 150 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 stop mode note 6 v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ). 2. i dd1 includes the peripheral operating current (except the current through the pull-up resistors of ports). 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. when the main system clock and subsystem clock are stopped. 538 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm000, prm010) of prescaler mode register 00 (prm00). selection of f sam = f x /2, f x /8, f x /512 is possible using bits 0 and 1 (prm001, prm011) of prescaler mode register 01 (prm01). however, if the ti000 or ti001 valid edge is selected as the count clock, the value becomes f sam = f x /8. parameter symbol conditions min. typ. max. unit cycle time t cy operating with 0.238 16 s (min. instruction main system clock 0.4 16 s execution time) 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti000, ti010, ti001, t tih0 , t til0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 2 s ti011 input high-/low- 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 2 s level width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 s width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s 4.0 v v dd 5.5 v 2.7 v v dd < 4.0 v 1.8 v v dd < 2.7 v 539 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 operation guaranteed range 16.0 cycle time t cy [ s] supply voltage v dd [v] 540 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 4.0 to 5.5 v) (1/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns input time from rd to wait t rdwt1 t cy 43 ns t rdwt2 t cy 43 ns input time from wr to wait t wrwt t cy 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy 15 ns delay time from t rdast 0.8t cy 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 541 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 2.7 to 4.0 v) (2/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns input time from rd to wait t rdwt1 t cy 75 ns t rdwt2 t cy 60 ns input time from wr to wait t wrwt t cy 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy 30 ns delay time from t rdast 0.8t cy 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 542 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (2) read/write operation (t a = 40 to +85 c, v dd = 1.8 to 2.7 v) (3/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns input time from rd to wait t rdwt1 t cy 350 ns t rdwt2 t cy 132 ns input time from wr to wait t wrwt t cy 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy 60 ns delay time from t rdast 0.8t cy 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) 543 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (3) serial interface (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) (a) sio3 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy1 4.0 v v dd 5.5 v 954 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/ t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 50 ns low-level width 1.8 v v dd < 4.0 v t kcy1 /2 100 ns si3 setup time t sik1 4.0 v v dd 5.5 v 100 ns (to sck3 ) 2.7 v v dd < 4.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3 hold time t ksi1 400 ns (from sck3 ) delay time from t kso1 c = 100 pf note 300 ns sck3 to so3 output note c is the load capacitance of the sck3 and so3 output lines. (b) sio3 3-wire serial i/o mode (sck3 ... external clock input) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy2 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/ t kh2 , t kl2 4.0 v v dd 5.5 v 400 ns low-level width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3 setup time t sik2 100 ns (to sck3 ) si3 hold time t ksi2 400 ns (from sck3 ) delay time from t kso2 c = 100 pf note 300 ns sck3 to so3 output note c is the load capacitance of the so3 output line. 544 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (c) csi1 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy3 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh3 , t kl3 4.0 v v dd 5.5 v t kcy3 /2 5ns width 2.7 v v dd < 4.0 v t kcy3 /2 20 ns 1.8 v v dd < 2.7 v t kcy3 /2 30 ns si1 setup time t sik3 25 ns (to sck1 ) si1 hold time t ksi3 110 ns (from sck1 ) delay time from sck1 t kso3 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the sck1 and so1 output lines. (d) csi1 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy4 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh4 , t kl4 4.0 v v dd 5.5 v 100 ns width 2.7 v v dd < 4.0 v 250 ns 1.8 v v dd < 2.7 v 500 ns si1 setup time t sik4 25 ns (to sck1 ) si1 hold time t ksi4 110 ns (from sck1 ) delay time from sck1 t kso4 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the so1 output line. (e) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps 2.7 v v dd < 4.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps 545 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (f) uart0 (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy5 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level t kh5 , t kl5 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (g) uart0 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps bit rate tolerance 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate (h) uart2 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps 2.7 v v dd < 4.0 v 156250 bps 1.8 v v dd < 2.7 v 62500 bps (i) uart2 (external clock input) parameter symbol conditions min. typ. max. unit asck2 cycle time t kcy6 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck2 high-/low-level t kh6 , t kl6 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.0 v 39063 bps 1.8 v v dd < 2.7 v 19531 bps 546 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud (j) uart2 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps bit rate tolerance 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate (k) i 2 c bus mode ( pd780076y, 780078y, 78f0078y only) parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f scl 0 100 0 400 khz bus free time t buf 4.7 1.3 s (between stop and start condition) hold time note 1 t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s start/restart condition setup time t su:sta 4.7 0.6 s data hold time cbus compatible master t hd:dat 5.0 s i 2 c bus 0 note 2 0 note 2 0.9 note 3 s data setup time t su:dat 250 100 note 4 ns sda0 and scl0 signal rise time t r 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 0.6 s capacitive load per each bus line cb 400 400 pf spike pulse width controlled by input filter t sp 050ns notes 1. on a start condition, the first clock pulse is generated after the hold period. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to internally provide an sda0 signal (with v ihmin. of the scl0 signal) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low hold time (t low ), only the maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in a standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. if the device does not extend the scl0 signal low state hold time t su:dat 250 ns if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb: total capacitance per bus line (unit: pf) 547 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud a/d converter characteristics (t a = 40 to +85 c, 2.2 v av ref v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 2.2 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.0 v av ref 5.5 v 14 96 s 2.7 v av ref < 4.0 v 19 96 s 2.2 v av ref < 2.7 v 28 96 s zero-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr full-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr integral linear error 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 2.2 v av ref < 2.7 v 8.5 lsb differential linear error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 2.2 v av ref < 2.7 v 3.5 lsb analog input impedance during sampling 100 k ? other than during sampling 10 m ? analog input voltage v ain 0av ref v av ref resistance r ref during a/d conversion 20 40 k ? note overall error excluding quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. remark fsr: full-scale range data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) and 0.1 30 a supply current feedback resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx s wait time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). 548 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud flash memory programming characteristics (t a = +10 to +40 c, v dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (1) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 4.0 v v dd 5.5 v 1.0 8.38 mhz 2.7 v v dd < 4.0 v 1.0 5.00 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when f x = 8.38 mhz v dd = 5.0 v 10% 24 ma v pp = v pp2 f x = 5.00 mhz v dd = 3.0 v 10% 12 ma v pp supply current i pp when v pp = v pp2 75 100 ma step erase time note 1 t er 0.99 1.0 1.01 s overall erase time per t era when step erase time = 1 s 20 s/area area note 2 step write time t wr 50 100 s overall write time per t wrw when step write time = 100 s 1000 s word note 3 number of rewrites per c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/area area note 4 notes 1. the recommended setting value of the step erase time is 1 s. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 4. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 1.0 s v pp pulse input start time from t rp 1.0 s reset v pp pulse high-/low-level width t pw 8.0 s v pp pulse input end time from t rpe 20 ms reset v pp pulse low-level input voltage v ppl 0.8v dd v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v 549 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud timing chart ac timing test points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti000, ti010, ti001, ti011 1/f ti5 t tih5 t til5 ti50, ti51 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 550 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud t rsl reset intp0 to intp3 t intl t inth interrupt request input timing reset input timing 551 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh 552 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 553 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr 554 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): t kcyn t khn t kln asck0, asck2 i 2 c bus mode ( scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r t low stop condition start condition stop condition restart condition remark n = 1 to 4 remark n = 5, 6 t kcyn t kln t khn sck1, sck3 si1, si3 so1, so3 t sikn t ksin t kson input data output data pd780076y, 780078y, 78f0078y only): 555 chapter 27 electrical specifications (conventional products) user s manual u14260ej3v1ud flash write mode setting timing notes 1. 3-wire serial i/o (sio3) type 2. i 2 c bus (iic0) type ( pd78f0078y only) 3. uart (uart0) type 4. handshake (when 3-wire serial i/o (sio3) type is used) v dd v dd 0 v v dd reset (input) 0 v v pph 0 v v pp v ppl t rp t pr t dp t pw t pw t rpe 0 v sck3 note 1 /scl0 note 2 0 v 0 v 0 v si3 note 1 /rxd0 note 3 so3 note 1 /txd0 note 3 /sda0 note 2 p31 (hs) note 4 reset command v il v il 556 user? manual u14260ej3v1ud chapter 28 package drawings remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 64-pin plastic lqfp (14x14) note each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.2 14.0 0.2 0.8 (t.p.) 1.0 j 17.2 0.2 k c 14.0 0.2 i 0.20 1.6 0.2 l 0.8 f 1.0 n p q 0.10 1.4 0.1 0.127 0.075 u 0.886 0.15 r s 3 1.7 max. t 0.25 p64gc-80-8bs h 0.37 + 0.08 ? 0.07 m 0.17 + 0.03 ? 0.06 s n j t detail of lead end c d a b k m i s p r l u q g f m h + 4 ? 3 1 64 49 17 32 16 48 33 s 557 chapter 28 package drawings user s manual u14260ej3v1ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 0.4 14.0 0.2 0.8 (t.p.) 1.0 j 17.6 0.4 k p64gc-80-ab8-5 c 14.0 0.2 i 0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.55 0.1 0.1 0.1 r s 5 5 2.85 max. h 0.37 + 0.08 ? 0.07 m 0.17 + 0.08 ? 0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h 558 chapter 28 package drawings user s manual u14260ej3v1ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1 559 user? manual u14260ej3v1ud chapter 29 recommended soldering conditions the pd780078, 780078y subseries should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 29-1. surface mounting type soldering conditions (1/2) (1) pd780076gc- -8bs: 64-pin plastic lqfp (14 14) pd780078gc- -8bs: 64-pin plastic lqfp (14 14) pd780076ygc- -8bs: 64-pin plastic lqfp (14 14) pd780078ygc- -8bs: 64-pin plastic lqfp (14 14) pd78f0078gc-8bs: 64-pin plastic lqfp (14 14) pd78f0078ygc-8bs: 64-pin plastic lqfp (14 14) pd780076gc- -ab8: 64-pin plastic qfp (14 14) pd780078gc- -ab8: 64-pin plastic qfp (14 14) pd780076ygc- -ab8: 64-pin plastic qfp (14 14) pd780078ygc- -ab8: 64-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-00-2 count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-00-2 count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (2) pd78f0078gc-ab8: 64-pin plastic qfp (14 14) pd78f0078ygc-ab8: 64-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-00-3 count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-00-3 count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). 560 chapter 29 recommended soldering conditions user? manual u14260ej3v1ud table 29-1. surface mounting type soldering conditions (2/2) (3) pd780076gk- -9et: 64-pin plastic tqfp (12 12) pd780078gk- -9et: 64-pin plastic tqfp (12 12) pd780076ygk- -9et: 64-pin plastic tqfp (12 12) pd780078ygk- -9et: 64-pin plastic tqfp (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-107-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-107-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-107-1 preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). (4) pd78f0078gk-9et: 64-pin plastic tqfp (12 12) pd78f0078ygk-9et: 64-pin plastic tqfp (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-103-2 count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-103-2 count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-103-1 preheating temperature: 120 c max. (package surface temperature), exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 561 user? manual u14260ej3v1ud appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries tables a-1 and a-2 show the major differences between the pd78018f, 780024a, 780034a, and 780078 subseries. table a-1. major differences between pd78018f, 780024a, 780034a, and 780078 subseries (hardware) name item emi noise reduction internal i 2 c bus version (y subseries) prom version flash memory version rom internal high-speed ram internal expansion ram minimum instruction execution time number of i/o ports timer a/d converter serial interface operating mode timer output package device file emulation board electrical specifications recommended soldering conditions pd78018f subseries note pd780024a, 780034a pd780078 subseries subseries not provided provided provided provided (multi-master supported) pd78p018f not provided not provided pd78f0034a, 78f0034b pd78f0078 8 kb to 60 kb 8 kb to 32 kb 48 kb, 60 kb 512, 1024 bytes 512, 1024 bytes 1024 bytes 512, 1024 bytes not provided 1024 bytes 0.4 s (10 mhz) 0.24 s (8.38 mhz), 0.16 s (12 mhz, expanded-specification products only) 53 51 52 16 bits: 1, 8 bits: 2, 16 bits: 1, 8 bits: 2, 16 bits: 2, 8 bits: 2, watch timer: 1, watch timer: 1, watch timer: 1, watchdog timer: 1 watchdog timer: 1 watchdog timer: 1 8 bits 8 8 bits 8 10 bits 8 ( pd780024a subseries) ?10 bits 8 ( pd780034a subseries) 3-wire/2-wire/sbi: 1, 3-wire: 2, uart: 1 3-wire: 1, uart: 1, 3-wire (automatic 3-wire/uart: 1 transmission/reception): 1 3-wire/2-wire/i 2 c: 1, 3-wire: 2, uart: 1, 3-wire: 1, uart: 1, 3-wire (automatic multi-master i 2 c: 1 3-wire/uart: 1, transmission/reception): 1 multi-master i 2 c: 1 3 (14-bit pwm output possible: 2) 3 (8-bit pwm output possible: 2) 4 (8-bit pwm output possible: 2) ? 64-pin sdip (19.05 mm (750)) ? 64-pin sdip (19.05 mm (750)) ?64-pin qfp (14 14) ?64-pin qfp (14 14) ?64-pin qfp (14 14) ?64-pin tqfp (12 12) ?64-pin lqfp (12 12) ?64-pin tqfp (12 12) ?64-pin lqfp (14 14) ?64-pin lqfp (14 14) ?64-pin lqfp (10 10) ?73-pin fbga (9 9) df78014 df780034 df780078 ie-78014-r-em-a, ie-780034-ns-em1 ie-780078-ns-em1 ie-78018-ns-em1 refer to the data sheet or user? manual (with electrical specifications) of each product. subseries without suffix y subseries with suffix y note maintenance product 562 appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries user? manual u14260ej3v1ud table a-2. major differences between pd78018f, 780024a, 780034a, and 780078 subseries (software) (1/2) name item a/d converter 16-bit timer/event counter interval timer pwm output ppg output pulse width measurement external event counter square wave output count clock control register output control register compare/capture register prescaler mode register capture/compare control register interrupt pd78018f subseries note 1 pd780024a, 780034a pd780078 subseries subseries take the appropriate measures for the first a/d conversion result immediately after the a/d conversion operation is started (adcs0 is set to 1), such as discarding it, because it may not satisfy the rating. however, if a wait time of 14 s (min.) has been secured after adce0 was set to 1 before starting operation (adcs0 is set to 1), the first data can be used. 1 ch 1 ch 2 ch tm0 tm0 tm00 tm01 f x /2, f x /2 2 , f x /2 3 , ti0 f x , f x /2 2 , f x /2 6 , ti00 f x , f x /2 2 ,f x /2, f x /2 3 f x /2 6 , ti000 f x /2 9 , ti001 tmc0 tmc0 tmc00 tmc01 toc0 toc0 toc00 toc01 cr00, cr01 (capture only) cr00, cr01 cr000, cr010 cr001, cr011 tcl0 note 2 prm0 prm00 prm01 crc0 crc00 crc01 inttm0 inttm00, inttm01 inttm000, inttm001, inttm010 inttm011 notes 1. maintenance product 2. tcl0: timer clock select register 0 563 appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries user? manual u14260ej3v1ud table a-2. major differences between pd78018f, 780024a, 780034a, and 780078 subseries (software) (2/2) name item 8-bit timer/event counter unit mode interval timer external event counter square wave output pwm output cascade connection mode interval timer external event counter square wave output count clock control register output control register clock select register interrupt pd78018f subseries note pd780024a, 780034a pd780078 subseries subseries 2 ch 2 ch tm1 tm2 tm50 tm51 tmc1 tmc50 tmc51 toc1 tmc50 tmc51 tcl1 tcl50 tcl51 inttm1 inttm2 inttm50 inttm51 f x /2 2 , f x /2 3 , f x /2 4 , f x /2 5 , f x /2 6 , f x /2 7 , f x /2 8 , f x /2 9 , f x /2 10 , f x 2 12 , ti1 f x /2 2 , f x /2 3 , f x /2 4 , f x /2 5 , f x /2 6 , f x /2 7 , f x /2 8 , f x /2 9 , f x /2 10 , f x /2 12 , ti2 f x , f x /2 2 , f x /2 4 , f x /2 6 , f x /2 8 , f x /2 10 , ti50 f x /2, f x /2 3 , f x /2 5 , f x /2 7 , f x /2 9 , f x /2 11 , ti51 note maintenance product 564 user? manual u14260ej3v1ud appendix b development tools the following development tools are available for the development of systems that employ the pd780078 and 780078y subseries. figure b-1 shows the development tool configuration. support for pc98-nx series unless otherwise specified, products compatible with ibm pc/at tm computers are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at computers. windows unless otherwise specified, ?indows?means the following oss. windows 3.1 windows 95 windows 98 windows 2000 windows nt tm ver.4.0 565 appendix b development tools user? manual u14260ej3v1ud figure b-1. development tool configuration (1/2) (1) when using the in-circuit emulator ie-78k0-ns or ie-78k0-ns-a notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ? software package ? project manager (windows only) note 2 software package flash memory write environment control software i/o board performance board power supply unit 566 appendix b development tools user s manual u14260ej3v1ud figure b-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-78001-r-a notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software ? assembler package ? c compiler package ? device file ? c compiler source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ? software package ? project manager (windows only) note 2 software package flash memory write environment control software i/o board emulation probe conversion board performance board 567 appendix b development tools user s manual u14260ej3v1ud b.1 software package sp78k0 this package contains various software tools for 78k/0 series development. software package the following tools are included. ra78k0, cc78k0, id78k0-ns, sm78k0, and various device files part number: s sp78k0 remark in the part number differs depending on the os used. s sp78k0 host machine os supply medium ab17 pc-9800 series, windows (japanese version) cd-rom bb17 ibm pc/at compatibles windows (english version) b.2 language processing software ra78k0 assembler package cc78k0 c compiler package df780078 note 1 device file cc78k0-l note 2 c library source file notes 1. the df780078 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, and rx78k0. 2. cc78k0-l is not included in the software package (sp78k0). this assembler converts programs written in mnemonics into object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with device file (df780078) (sold separately). 568 appendix b development tools user s manual u14260ej3v1ud remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df780078 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt b.3 control software project manager this is control software designed to enable efficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. 569 appendix b development tools user s manual u14260ej3v1ud b.5 debugging tools (hardware) b.5.1 when using the in-circuit emulator ie-78k0-ns or ie-78k0-ns-a ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780078-ns-em1 emulation board np-64gc emulation probe ev-9200gc-64 conversion socket (see figures b-2 and b-3 ) np-64gc-tq np-h64gc-tq emulation probe tgc-064sap conversion adapter np-64gk np-h64gk-tq emulation probe tgk-064sbw conversion adapter (see figure b-4 ) remarks 1. np-64cw, np-64gc, np-64gc-tq, np-h64gc-tq, np-64gk, and np-h64gk-tq are products of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgk-064sbw and tgc-064sap are products of tokyo eletech corporation. contact: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. 3. ev-9200gc-64 is sold in five-unit sets. 4. tgk-064sbw and tgc-064sap are sold in single units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. a combination of the ie-78k0-ns and ie-78k0-ns-pa. this adapter is used for supplying power from a receptacle of 100 v to 240 v ac. this adapter is required when using a pc-9800 series computer (except notebook type) as the host machine (c bus compatible). this is pc card and interface cable required when using a notebook-type computer as the host machine (pcmcia socket compatible). this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). this adapter is required when using a computer with a pci bus as the host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion socket connects the np-64gc to a target system board designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion adapter connects the np-64gc-tq or np-h64gk-tq to a target system board designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic tqfp (gk-9et type). this conversion adapter connects the np-64gk or np-h64gk-tq to a target system board designed for a 64-pin plastic tqfp (gk-9et type). 570 appendix b development tools user s manual u14260ej3v1ud b.5.2 when using the in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780078-ns-em1 emulation board ie-78k0-r-ex1 emulation probe conversion board ep-78240gc-r note emulation probe ev-9200gc-64 conversion socket (see figures b-2 and b-3 ) ep-78012gk-r emulation probe tgk-064sbw conversion adapter (see figure b-4 ) note maintenance product remarks 1. tgk-064sbw is a product of tokyo eletech corporation. contact: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. 2. ev-9200gc-64 is sold in five-unit sets. 3. tgk-064sbw is sold in single units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to the integrated debugger (id78k0). this emulator should be used in combination with an emulation probe and interface adapter, which is required to connect this emulator to the host machine. this adapter is required when using a pc-9800 series computer (except notebook type) as the host machine (c bus compatible). this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). this adapter is required when using a computer with a pci bus as the host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator and emulation probe conversion board. this board is required when using the ie-780078-ns-em1 on the ie-78001-r-a. this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion socket connects the ep-78240gc-r to a target system board designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic tqfp (gk-9et type). this conversion adapter connects the ep-78012gk-r to a target system board designed for a 64-pin plastic tqfp (gk-9et type). 571 appendix b development tools user s manual u14260ej3v1ud b.6 debugging tools (software) sm78k0 this is a system simulator for the 78k/0 series. the sm78k0 is windows-based system simulator software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df780078) (sold separately). part number: s sm78k0 id78k0-ns this debugger supports the in-circuit emulators for the 78k/0 series. the integrated debugger id78k0-ns is windows-based software. (supporting in-circuit emulators it has improved c-compatible debugging functions and can display the results of ie-78k0-ns and ie-78k0-ns-a) tracing with the source program using an integrating window function that associates id78k0 the source program, disassemble display, and memory display with the trace result. integrated debugger it should be used in combination with the device file (sold separately). (supporting in-circuit emulator ie-78001-r-a) part number: s id78k0-ns, s id78k0 remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0 host machine os supply medium ab13 ibm pc/at compatibles windows (japanese version) 3.5-inch 2hd fd bb13 windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 572 appendix b development tools user s manual u14260ej3v1ud conversion socket (ev-9200gc-64) package drawing and recommended board mounting pattern figure b-2. ev-9200gc-64 package drawing (for reference only) a f 1 e ev-9200gc-64 b d c m n l k r q i h p o s t j g no.1 pin index ev-9200gc-64-g0e item millimeters inches a b c d e f g h i j k l m n o p q r s t 18.8 14.1 14.1 18.8 4-c 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.74 0.555 0.555 0.74 4-c 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 0.005 573 appendix b development tools user s manual u14260ej3v1ud figure b-3. ev-9200gc-64 recommended board mounting pattern (for reference only) f e d g h i j k l c b a 0.031 0.591=0.472 0.031 0.591=0.472 ev-9200gc-64-p1e item millimeters inches a b c d e f g h i j k l 19.5 14.8 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 2.36 0.03 2.2 0.1 1.57 0.03 0.768 0.583 0.583 0.768 0.236 0.236 0.197 0.093 0.087 0.062 0.8 0.02 15=12.0 0.05 0.8 0.02 15=12.0 0.05 +0.002 0.001 +0.003 0.002 +0.002 0.001 +0.003 0.002 +0.004 0.003 +0.004 0.003 +0.001 0.002 +0.001 0.002 +0.004 0.005 +0.001 0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mount manual" (http://www.necel.com/pkg/en/mount/index. html). caution 574 appendix b development tools user s manual u14260ej3v1ud conversion adapter (tgk-064sbw) package drawing figure b-4. tgk-064sbw package drawing (for reference only) item millimeters inches b 1.85 0.073 c 3.5 0.138 a 0.3 0.012 d 2.0 0.079 h 5.9 0.232 i 0.8 0.031 j 2.4 0.094 e 3.9 0.154 f 1.325 g 1.325 0.052 0.052 item millimeters inches b 0.65x15=9.75 0.026x0.591=0.384 c 0.65 0.026 a 18.4 0.724 d h 0.65x15=9.75 0.026x0.591=0.384 i 11.85 0.467 j 18.4 0.724 e 10.15 0.400 f 12.55 0.494 k c 2.0 c 0.079 l 12.45 0.490 m q 11.1 0.437 r 1.45 0.057 s 1.45 0.057 n 7.7 0.303 o 10.02 p 14.92 0.587 0.394 w 5.3 0.209 x 4-c 1.0 4-c 0.039 y 3.55 0.140 t 4- 1.3 4- 0.051 u 1.8 v 5.0 0.197 0.071 z 0.9 0.035 7.75 10.25 0.305 0.404 g 14.95 0.589 k 2.7 0.106 tgk-064sbw-g1e ? h a h a g z c l q n b c i j k g f e d m x r s w o p protrusion height u t v k j i y e d b f note product by tokyo eletech corporation. 575 user? manual u14260ej3v1ud appendix c notes on target system design the following shows the conditions when connecting the emulation probe and conversion adapter. consider the shape of the components to be mounted on the target system and follow the configurations below when designing the system. among the products described in this appendix, np-64gc-tq, np-h64gc-tq, np-64gk, and np-h64gk-tq are products of naito densei machida mfg. co., ltd. and tgc-064sap and tgk-064sbw are products of tokyo eletech corporation. table c-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-64gc-tq tgc-064sap 170 mm np-h64gc-tq 370 mm np-64gk tgk-064sbw 170 mm np-h64gk-tq 370 mm 576 appendix c notes on target system design user? manual u14260ej3v1ud figure c-1. distance between in-circuit emulator and conversion adapter (64gc) note the above distance shows when the np-64gc-tq is used. when the np-h64gc-tq is used, the distance is 370 mm. figure c-2. connection conditions of target system (np-64gc-tq) emulation probe np-64gc-tq emulation board ie-780078-ns-em1 23 mm 25 mm 40 mm 34 mm target system 20.65 mm pin 1 11 mm 20.65 mm conversion adapter tgc-064sap 170 mm note in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780078-ns-em1 conversion adapter: tgc-064sap target system emulation probe np-64gc-tq, np-h64gc-tq 577 appendix c notes on target system design user s manual u14260ej3v1ud figure c-3. connection conditions of target system (np-h64gc-tq) emulation probe np-h64gc-tq emulation board ie-780078-ns-em1 23 mm 23 mm 42 mm 45 mm 20.65 mm target system 20.65 mm pin 1 11 mm conversion adapter tgc-064sap 578 appendix c notes on target system design user s manual u14260ej3v1ud figure c-4. distance between in-circuit emulator and conversion adapter (64gk) note the above distance shows when the np-64gk is used. when the np-h64gk-tq is used, the distance is 370 mm. figure c-5. connection conditions of target system (np-64gk) emulation probe np-64gk emulation board ie-780078-ns-em1 21.95 mm 40 mm 34 mm target system 18.4 mm pin 1 11 mm 25 mm 18.4 mm conversion adapter tgk-064sbw 170 mm note in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780078-ns-em1 conversion adapter tgk-064sbw target system emulation probe np-64gk, np-h64gk-tq 579 appendix c notes on target system design user s manual u14260ej3v1ud figure c-6. connection conditions of target system (np-h64gk-tq) emulation probe np-h64gk-tq emulation board ie-780078-ns-em1 42 mm 45 mm 18.4 mm 11 mm target system 18.4 mm pin 1 21.95 mm 23 mm conversion adapter tgk-064sbw 580 users manual u14260ej3v1ud appendix d register index d.1 register index (in alphabetical order with respect to register names) [a] a/d conversion result register 0 (adcr0) 231 a/d converter mode register 0 (adm0) 228 analog input channel specification register 0 (ads0) 231 asynchronous serial interface mode register 0 (asim0) 250 asynchronous serial interface mode register 2 (asim2) 272 asynchronous serial interface status register 0 (asis0) 252 asynchronous serial interface status register 2 (asis2) 274 asynchronous serial interface transmit status register 2 (asif2) ... 275 [b] baud rate generator control register 0 (brgc0) 252 baud rate generator control register 2 (brgc2) ... 276 [c] capture/compare control register 00 (crc00) 151 capture/compare control register 01 (crc01) ... 151 clock output select register (cks) 221 clock select register 2 (cksel2) ... 277 [e] 8-bit timer compare register 50 (cr50) 190 8-bit timer compare register 51 (cr51) 190 8-bit timer counter 50 (tm50) 189 8-bit timer counter 51 (tm51) 189 8-bit timer mode control register 50 (tmc50) 192 8-bit timer mode control register 51 (tmc51) 192 external interrupt falling edge enable register (egn) 404 external interrupt rising edge enable register (egp) 404 [i] iic control register 0 (iicc0) 338 iic shift register 0 (iic0) 336 iic status register 0 (iics0) 343 iic transfer clock select register 0 (iiccl0) 346 internal expansion ram size switching register (ixs) ... 440 interrupt mask flag register 0h (mk0h) 402 interrupt mask flag register 0l (mk0l) 402 interrupt mask flag register 1l (mk1l) 402 interrupt request flag register 0h (if0h) 401 interrupt request flag register 0l (if0l) 401 interrupt request flag register 1l (if1l) 401 581 appendix d register index users manual u14260ej3v1ud [m] memory expansion mode register (mem) 418 memory expansion wait setting register (mm) 419 memory size switching register (ims) 439 [o] oscillation stabilization time select register (osts) 132, 427 [p] port mode register 0 (pm0) 118 port mode register 2 (pm2) 118, 254, 322 port mode register 3 (pm3) 118, 280, 313, 347 port mode register 4 (pm4) 118 port mode register 5 (pm5) 118 port mode register 6 (pm6) 118 port mode register 7 (pm7) 118, 157, 195, 223 port mode register 8 (pm8) ... 118, 322 port register 0 (p0) 122 port register 1 (p1) 122 port register 2 (p2) 122 port register 3 (p3) 122 port register 4 (p4) 122 port register 5 (p5) 122 port register 6 (p6) 122 port register 7 (p7) 122 port register 8 (p8) ... 122 prescaler mode register 00 (prm00) 155 prescaler mode register 01 (prm01) ... 155 priority specification flag register 0h (pr0h) 403 priority specification flag register 0l (pr0l) 403 priority specification flag register 1l (pr1l) 403 processor clock control register (pcc) 129 program status word (psw) 72, 405 pull-up resistor option register 0 (pu0) 123 pull-up resistor option register 2 (pu2) 123 pull-up resistor option register 3 (pu3) 123 pull-up resistor option register 4 (pu4) 123 pull-up resistor option register 5 (pu5) 123 pull-up resistor option register 6 (pu6) 123 pull-up resistor option register 7 (pu7) 123 pull-up resistor option register 8 (pu8) ... 123 [r] receive buffer register 0 (rxb0) 249 receive buffer register 2 (rxb2) ... 270 582 appendix d register index users manual u14260ej3v1ud [s] serial clock select register 1 (csic1) ... 321 serial i/o shift register 1 (sio1) 319 serial i/o shift register 3 (sio3) 311 serial operation mode register 1 (csim1) 320 serial operation mode register 3 (csim3) 311 16-bit timer capture/compare register 000 (cr000) 145 16-bit timer capture/compare register 001 (cr001) ... 145 16-bit timer capture/compare register 010 (cr010) 147 16-bit timer capture/compare register 011 (cr011) ... 147 16-bit timer counter 00 (tm00) 145 16-bit timer counter 01 (tm01) 145 16-bit timer mode control register 00 (tmc00) 148 16-bit timer mode control register 01 (tmc01) ... 148 16-bit timer output control register 00 (toc00) 153 16-bit timer output control register 01 (toc01) ... 153 slave address register 0 (sva0) 336 [t] timer clock select register 50 (tcl50) 191 timer clock select register 51 (tcl51) 191 transfer mode specification register 2 (trmc2) ... 279 transmit buffer register 1 (sotb1) ... 319 transmit buffer register 2 (txb2) ... 270 transmit shift register 0 (txs0) 249 [w] watch timer operation mode register (wtm) 211 watchdog timer clock select register (wdcs) 216 watchdog timer mode register (wdtm) 217 583 appendix d register index users manual u14260ej3v1ud d.2 register index (in alphabetical order with respect to register symbol) [a] adcr0: a/d conversion result register 0 231 adm0: a/d converter mode register 0 228 ads0: analog input channel specification register 0 231 asif2: asynchronous serial interface transmit status register 2 ... 275 asim0: asynchronous serial interface mode register 0 250 asim2: asynchronous serial interface mode register 2 ... 272 asis0: asynchronous serial interface status register 0 252 asis2: asynchronous serial interface status register 2 ... 274 [b] brgc0: baud rate generator control register 0 252 brgc2: baud rate generator control register 2 ... 276 [c] cks: clock output select register 221 cksel2: clock select register 2 ... 277 cr000: 16-bit timer capture/compare register 000 145 cr001: 16-bit timer capture/compare register 001 ... 145 cr010: 16-bit timer capture/compare register 010 147 cr011: 16-bit timer capture/compare register 011 ... 147 cr50: 8-bit timer compare register 50 190 cr51: 8-bit timer compare register 51 190 crc00: capture/compare control register 00 151 crc01: capture/compare control register 01 ... 151 csic1: serial clock select register 1 ... 321 csim1: serial operation mode register 1 320 csim3: serial operation mode register 3 311 [e] egn: external interrupt falling edge enable register 404 egp: external interrupt rising edge enable register 404 [i] if0h: interrupt request flag register 0h 401 if0l: interrupt request flag register 0l 401 if1l: interrupt request flag register 1l 401 iic0: iic shift register 0 336 iicc0: iic control register 0 338 iiccl0: iic transfer clock select register 0 346 iics0: iic status register 0 343 ims: memory size switching register 439 ixs: internal expansion ram size switching register ... 440 584 appendix d register index users manual u14260ej3v1ud [m] mem: memory expansion mode register 418 mk0h: interrupt mask flag register 0h 402 mk0l: interrupt mask flag register 0l 402 mk1l: interrupt mask flag register 1l 402 mm: memory expansion wait setting register 419 [o] osts: oscillation stabilization time select register 132, 427 [p] p0: port register 0 122 p1: port register 1 122 p2: port register 2 122 p3: port register 3 122 p4: port register 4 122 p5: port register 5 122 p6: port register 6 122 p7: port register 7 122 p8: port register 8 ... 122 pcc: processor clock control register 129 pm0: port mode register 0 118 pm2: port mode register 2 118, 254, 322 pm3: port mode register 3 118, 280, 313, 347 pm4: port mode register 4 118 pm5: port mode register 5 118 pm6: port mode register 6 118 pm7: port mode register 7 118, 157, 195, 223 pm8: port mode register 8 ... 118, 322 pr0h: priority specification flag register 0h 403 pr0l: priority specification flag register 0l 403 pr1l: priority specification flag register 1l 403 prm00: prescaler mode register 00 155 prm01: prescaler mode register 01 ... 155 psw: program status word 72, 405 pu0: pull-up resistor option register 0 123 pu2: pull-up resistor option register 2 123 pu3: pull-up resistor option register 3 123 pu4: pull-up resistor option register 4 123 pu5: pull-up resistor option register 5 123 pu6: pull-up resistor option register 6 123 pu7: pull-up resistor option register 7 123 pu8: pull-up resistor option register 8 ... 123 [r] rxb0: receive buffer register 0 249 rxb2: receive buffer register 2 ... 270 585 appendix d register index users manual u14260ej3v1ud [s] sio1: serial i/o shift register 1 319 sio3: serial i/o shift register 3 311 sotb1: transmit buffer register 1 ... 319 sva0: slave address register 0 336 [t] tcl50: timer clock select register 50 191 tcl51: timer clock select register 51 191 tm00: 16-bit timer counter 00 145 tm01: 16-bit timer counter 01 ... 145 tm50: 8-bit timer counter 50 189 tm51: 8-bit timer counter 51 189 tmc00: 16-bit timer mode control register 00 148 tmc01: 16-bit timer mode control register 01 ... 148 tmc50: 8-bit timer mode control register 50 192 tmc51: 8-bit timer mode control register 51 192 toc00: 16-bit timer output control register 00 153 toc01: 16-bit timer output control register 01 ... 153 trmc2: transfer mode specification register 2 ... 279 txb2: transmit buffer register 2 ... 270 txs0: transmit shift register 0 249 [w] wdcs: watchdog timer clock select register 216 wdtm: watchdog timer mode register 217 wtm: watch timer operation mode register 211 586 user? manual u14260ej3v1ud appendix e revision history e.1 major revisions in this edition (1/3) page description u14260ej3v0ud00 u14260ej3v1ud00 p. 360 modification of figure 18-18 communication reservation timing p. 366 modification of figure 18-21 master operation flowchart (5/5) pp. 443, 444 division of note in previous edition of figure 23-5 example of connection with dedicated flash programmer to notes 1 and 2 and modification of contents p. 447 addition of description on voltage monitoring of dedicated flash programmer to 587 appendix e revision history user? manual u14260ej3v1ud (2/3) page description modification of the following figures p. 159 ? figure 8-17 timing of interval timer operation p. 175 ? figure 8-36 ppg output operation timing p. 183 ? figure 8-37 start timing of 16-bit timer counter 0n (tm0n) addition of the following figures p. 189 ? figure 9-3 format of 8-bit timer counter 5n (tm5n) p. 190 ? figure 9-4 format of 8-bit timer compare register 5n (cr5n) modification of the following figures pp. 196 to 198 ? figure 9-10 interval timer operation timing p. 199 ? figure 9-11 external event counter operation timing (with rising edge specified) p. 201 ? figure 9-12 square-wave output operation timing p. 203 ? figure 9-13 pwm output operation timing p. 204 ? figure 9-14 timing of operation with cr5n changed p. 205 ? figure 9-15 16-bit resolution cascade connection mode p. 209 ? figure 9-16 start timing of 8-bit timer counter 5n (tm5n) p. 202 modification of description on cycle and duty, and addition of active level width to 9.4.4 8-bit pwm output operation p. 214 addition of 10.5 cautions for watch timer and figure 10-4 example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) p. 225 modification of figure 13-1 block diagram of 10-bit a/d converter p. 226 modification of part of description in 13.2 a/d converter configuration p. 228 shift of description of a/d conversion result register 0 (adcr0) to 13.3 registers used in a/d converter p. 232 modification of part of description in 13.4.1 basic operations of a/d converter p. 234 addition of description of successive approximation register (sar) to 13.4.2 input voltage and conversion results modification of the following figures p. 236 ? figure 13-9 a/d conversion by hardware start (when falling edge is specified) p. 237 ? figure 13-10 a/d conversion by software start p. 242 ? figure 13-17 a/d conversion end interrupt request generation timing p. 243 modification of part of description in (10) timing at which a/d conversion result is undefined in 13.6 cautions for a/d converter p. 245 addition of figure 13-20 timing of a/d converter sampling and a/d conversion start delay p. 255 modification of description in (1) registers to be used in 14.4.2 asynchronous serial interface (uart) mode p. 259 addition of figure 14-9 example of uart transmit/receive data waveform p. 263 modification of table 14-4 causes of receive errors p. 264 modification of description in (1) registers to be used in 14.4.3 infrared data transfer mode p. 282 modification of description in (1) registers to be used in 15.4.2 asynchronous serial interface (uart) mode p. 287 addition of figure 15-12 example of uart transmit/receive data waveform p. 295 modification of table 15-9 causes of receive errors p. 297 modification of description in (1) registers to be used in 15.4.3 multi-processor transfer mode p. 303 modification of description in (1) registers to be used in 15.4.4 infrared data transfer (irda) mode 588 appendix e revision history user? manual u14260ej3v1ud (3/3) page description p. 315 modification of description in (1) registers to be used in 16.4.2 3-wire serial i/o mode p. 317 modification of table 16-3 register settings p. 319 partial modification of figure 17-1 block diagram of serial interface csi1 p. 321 partial modification of figure 17-3 format of serial clock select register 1 (csic1) p. 324 modification of description in (1) registers to be used in 17.4.2 3-wire serial i/o mode p. 331 addition of (5) so1 output to 17.4.2 3-wire serial i/o mode pp. 362 to 366 modification of figure 18-21 master operation flowchart p. 367 modification of (2) slave operation in 18.5.15 communication operations p. 404 addition of table 19-3 ports corresponding to egpn and egnn p. 406 modification of part of description in 19.4.1 non-maskable interrupt request acknowledgment operation p. 409 modification of part of description in 19.4.2 maskable interrupt request acknowledgment operation p. 419 addition of note to figure 20-2 format of memory expansion mode register (mem) and addition of figure 20-3 pins specified for address (with pd780076 and 780076y) p. 442 partial modification of table 23-3 communication mode list p. 467 revision of chapter 25 electrical specifications (expanded-specification products of pd780076, 780078, 78f0078) p. 498 addition of chapter 26 electrical specifications (expanded-specification products of pd780076y, 780078y, 78f0078y) p. 527 revision of chapter 27 electrical specifications (conventional products) p. 559 partial modification of table 29-1 surface mounting type soldering conditions pp. 564, 565 deletion of b.7 embedded software and b.8 system upgrade from former in-circuit emulator for in previous edition 78k/0 series to ie-78001-r-a in the previous edition 589 appendix e revision history user? manual u14260ej3v1ud e.2 revision history up to previous edition the history of revisions made up to this edition is shown below. (1/4) edition contents applied to: 2nd addition of the following package ? 64-pin plastic lqfp (gc-8bs type) addition of expanded-specification products to the pd780078 subseries addition of 1.1 expanded-specification products and conventional products modification of voltage operation range of a/d converter in 1.8 outline of functions modification of voltage operation range of a/d converter in 2.7 outline of functions addition of description about pin processing in 3.2.17 v pp (flash memory version only) modification of i/o circuit types of p32 and p33 in table 3-1 pin i/o circuit types addition of description about pin processing in 4.2.17 v pp (flash memory version only) addition of description about programming area in 5.1.2 (1) internal high-speed ram and (2) internal expansion ram modification of figure 5-10 data to be saved to stack memory and figure 5-11 data to be restored from stack memory modification of [description example] in 5.4.4 short direct addressing addition of [illustration] in 5.4.7 based addressing, 5.4.8 based indexed addressing, and 5.4.9 stack addressing modification of port block diagrams ( figure 6-2 block diagram of p00 to p03 to figure 6-21 block diagram of p80 ) addition of table 6-6 port mode registers and output latch setting when alternate function is used addition of description of internal feedback resistor and oscillation stabilization time select register (osts) in 7.3 clock generator control register deletion of 8.5.6 one-shot pulse output operation in the previous edition modification of figure 8-1 block diagram of 16-bit timer/event counter 00 and figure 8-2 block diagram of 16-bit timer/event counter 01 change of table 8-2 ti00n pin valid edge and cr00n, cr01n capture trigger and table 8-3 ti01n pin valid edge and cr00n capture trigger in the previous edition to table 8-2 cr00n capture trigger and valid edges of ti00n and ti01n pins and table 8-3 cr01n capture trigger and valid edge of ti00n pin (crc02n = 1) change of explanation order of each function in 8.4 operation of 16-bit timer/ event counters 00, 01 addition of figure 8-31 ppg output configuration diagram and figure 8-32 ppg output operation timing throughout chapter 1 outline ( pd780078 subseries) chapter 2 outline ( pd780078y subseries) chapter 3 pin function ( pd780078 subseries) chapter 4 pin function ( pd780078y subseries) chapter 5 cpu architecture chapter 6 port functions chapter 7 clock generator chapter 8 16-bit timer/event counters 00, 01 590 appendix e revision history user? manual u14260ej3v1ud (2/4) edition contents applied to: 2nd addition of 8.5 program list modification of 8.6 (3) capture register data retention timing addition of (11) stop mode or main system clock stop mode setting modification of figure 9-1 block diagram of 8-bit timer/event counter 50 and figure 9-2 block diagram of 8-bit timer/event counter 51 deletion of caution in figure 9-5 format of 8-bit timer mode control register 50 (tmc50) and figure 9-6 format of 8-bit timer mode control register 51 (tmc51) addition of [setting] in 9.4.2 external event counter operation addition of description about frequency to [setting] in 9.4.3 square-wave output (8-bit resolution) operation addition of descriptions about frequency and duty ratio to [setting] in 9.4.4 8-bit pwm output operation addition of 9.5 program list deletion of 9.6 (2) operation after compare register transition during timer count operation in the previous edition deletion of oscillation stabilization time select register (osts) from 11.4 registers to control watchdog timer in the previous edition modification of figure 12-1 block diagram of clock output/buzzer output controller addition of figure 13-2 format of a/d conversion result register 0 (adcr0) modification of description in 13.2 (3) sample & hold circuit and (4) voltage comparator , and addition of (9) adtrg pin addition of table 13-2 adcs0 and adce0 settings and figure 13-4 timing chart when boost reference voltage generator is used addition of table 13-3 sampling time and a/d conversion start delay time of a/d converter deletion of 13.6 (4) noise countermeasures (those deleted are added to figure 13-20 example of connecting capacitor to av ref pin and figure 13-22 example of connection when signal source impedance is high ) addition of (13) input impedance of ani0 to ani7 pins modification of figure 14-1 block diagram of serial interface uart0 shift of description about asynchronous serial interface status register 0 (asis0) from 14.3 registers to control serial interface uart0 to 14.2 configuration of serial interface uart0 addition of caution in figure 14-7 error tolerance (when k = 0), including sampling errors modification of caution in figure 14-10 timing of asynchronous serial interface receive completion interrupt request addition of (1) registers to be used and (3) relationship between main system clock and baud rate in 14.4.3 infrared data transfer mode addition of table 14-6 register settings chapter 8 16-bit timer/event counters 00, 01 chapter 9 8-bit timer/ event counters 50, 51 chapter 11 watchdog timer chapter 12 clock output/buzzer output controller chapter 13 a/d converter chapter 14 serial interface uart0 591 appendix e revision history user? manual u14260ej3v1ud (3/4) edition contents applied to: 2nd modification of figure 15-1 block diagram of serial interface uart2 shift of descriptions about asynchronous serial interface status register 2 (asis2) and asynchronous serial interface transmit status register 2 (asif2) from 15.3 registers to control serial interface uart2 to 15.2 configuration of serial interface uart2 modification of caution 1 and addition of cautions 2 and 3 in figure 15-4 format of asynchronous serial interface transmit status register 2 (asif2) addition of notes 7 and 8 in figure 15-8 format of transfer mode specification register 2 (trmc2) modification of error values in table 15-2 relationship between main system clock and baud rate addition of caution in table 15-3 maximum permissible baud rate error and minimum permissible baud rate error modification of the intst2 timing in (ii) and (iii) of figure 15-12 timing of asynchronous serial interface transmit completion interrupt request division of table 15-6 transmission status and writing to txb2 in the previous edition into table 15-4 writing to txbf and txb2 (when successive transmission is started) and table 15-5 writing to txsf and txb2 (when successive transmission is in progress) modification of figure 15-14 timing of starting successive transmission modification of figure 15-15 timing of completing successive transmission modification of figure 15-17 receive error timing addition of table 15-10 register settings modification of figure 16-1 block diagram of serial interface sio3 addition of notes 3 and 4 in figure 16-2 format of serial operation mode register 3 (csim3) addition of table 16-2 register settings modification of figure 17-1 block diagram of serial interface csi1 addition of description about ss1 pin in 17.4.2 (2) communication operation modification of figure 17-6 timing of 3-wire serial i/o mode modification of figure 17-8 output operation of first bit modification of figure 17-9 output value of so1 pin (last bit) deletion of 17.4.2 (6) sck1 pin and (7) so1 pin in the previous edition addition of table 17-2 register settings modification of figure 18-1 block diagram of serial interface iic0 incorporation of 18.3 (4) iic shift register 0 (iic0) and (5) slave address register 0 (sva0) in the previous edition into 18.2 (1) iic shift register 0 (iic0) and (2) slave address register 0 (sva0) , respectively addition of description to transfer lines ?in figure 18-16 wait signal addition of descriptions to notes 1 and 2 in table 18-2 intiic0 timing and wait control modification of figure 18-21 master operation flowchart and figure 18-22 slave operation flowchart chapter 15 serial interface uart2 chapter 16 serial interface sio3 chapter 17 serial interface csi1 chapter 18 serial interface iic0 ( pd780078y subseries only) 592 appendix e revision history user? manual u14260ej3v1ud (4/4) edition contents applied to: 2nd modification of 18.5.16 (3) (d) (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) modification of (1) start condition ~ address and (2) data in figure 18-23 example of master to slave communication (when 9-clock wait is selected for both master and slave) modification of figure 18-24 example of slave to master communication (when 9-clock wait is selected for both master and slave) modification of (e) software interrupt in figure 19-1 basic configuration of interrupt function addition of cautions 3 and 4 in figure 19-2 format of interrupt request flag register (if0l, if0h, if1l) addition of caution in figure 19-5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) addition of description and remark in 19.4.1 non-maskable interrupt request acknowledgment operation addition of description in 19.4.2 maskable interrupt acknowledgment operation addition of item to table 19-4 interrupt requests enabled for multiple interrupt servicing addition of description about when using expanded-specification products addition of clock output and buzzer output in table 21-1 halt mode operating statuses modification of clock output in table 21-3 stop mode operating statuses modification of chapter addition of chapters addition of table a-2 major differences between pd78018f, 780024a, 780034a, and 780078 subseries (software) modification of chapter addition of chapters chapter 18 serial interface iic0 ( pd780078y subseries only) chapter 19 interrupt functions chapter 20 external device expansion function chapter 21 standby function chapter 23 pd78f0078, 78f0078y chapter 25 electrical specifications chapter 26 package drawings chapter 27 recommended soldering conditions appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries appendix b development tools appendix c notes on target system design appendix e revision history |
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